Tool/software: Code Composer Studio
We have developed a secondary boot-loader that downloads application images over CAN bus.
I wish to verify the downloaded image and it seems that a linker generated CRC table data object is the way to go.
I am using "Example_2806xLEDBlink" as a test application for downloading.
I have managed to get a linker command file to generate the CRC table but only for the ".text" section of "Example_2806xLEDBlink".
The application gets downloaded in the 6 different blocks that "hex200.exe" creates.
"Example_2806xLEDBlink.out" .TI.crctab ==> (BOOT TABLE)
"Example_2806xLEDBlink.out" .scn_1 ==> (BOOT TABLE)
"Example_2806xLEDBlink.out" .cinit ==> (BOOT TABLE)
"Example_2806xLEDBlink.out" .text ==> (BOOT TABLE)
"Example_2806xLEDBlink.out" codestart ==> (BOOT TABLE)
"Example_2806xLEDBlink.out" ramfuncs ==> (BOOT TABLE)
"Example_2806xLEDBlink.out" .econst ==> (BOOT TABLE)
So my question is: how to create a CRC table record for each of these blocks?
I have tried every which way but just can't seem to get the syntax correct.
My linker file follows:
MEMORY
{
PAGE 0 : /* Program Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
RAML0 : origin = 0x008000, length = 0x000800 /* on-chip RAM block L0 */
RAML1 : origin = 0x008800, length = 0x000400 /* on-chip RAM block L1 */
OTP : origin = 0x3D7800, length = 0x000400 /* on-chip OTP */
BEGIN : origin = 0x3D8000, length = 0x000002 /* Part of FLASHH. Used for secondary bootloader Sboot. */
CRC_TABLE : origin = 0x3D8002, length = 0x000080 /* Part of FLASHH. Used for CRC table. */
FLASHH : origin = 0x3D8082, length = 0x003F7E /* on-chip FLASH */
FLASHG : origin = 0x3DC000, length = 0x004000 /* on-chip FLASH */
FLASHF : origin = 0x3E0000, length = 0x004000 /* on-chip FLASH */
FLASHE : origin = 0x3E4000, length = 0x004000 /* on-chip FLASH */
FLASHD : origin = 0x3E8000, length = 0x004000 /* on-chip FLASH */
FLASHC : origin = 0x3EC000, length = 0x004000 /* on-chip FLASH */
FLASHA : origin = 0x3F4000, length = 0x003F80 /* on-chip FLASH */
CSM_RSVD : origin = 0x3F7F80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
CSM_PWL_P0 : origin = 0x3F7FF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
FPUTABLES : origin = 0x3FD590, length = 0x0006A0 /* FPU Tables in Boot ROM */
IQTABLES : origin = 0x3FDF00, length = 0x000B50 /* IQ Math Tables in Boot ROM */
IQTABLES2 : origin = 0x3FEA50, length = 0x00008C /* IQ Math Tables in Boot ROM */
IQTABLES3 : origin = 0x3FEADC, length = 0x0000AA /* IQ Math Tables in Boot ROM */
ROM : origin = 0x3FF3B0, length = 0x000C10 /* Boot ROM */
RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */
VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */
PAGE 1 : /* Data Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
/* Registers remain on PAGE1 */
BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */
RAMM0 : origin = 0x000050, length = 0x0003B0 /* on-chip RAM block M0 */
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
RAML2 : origin = 0x008C00, length = 0x000400 /* on-chip RAM block L2 */
RAML3 : origin = 0x009000, length = 0x001000 /* on-chip RAM block L3 */
RAML4 : origin = 0x00A000, length = 0x002000 /* on-chip RAM block L4 */
RAML5 : origin = 0x00C000, length = 0x002000 /* on-chip RAM block L5 */
RAML6 : origin = 0x00E000, length = 0x002000 /* on-chip RAM block L6 */
RAML7 : origin = 0x010000, length = 0x002000 /* on-chip RAM block L7 */
RAML8 : origin = 0x012000, length = 0x002000 /* on-chip RAM block L8 */
USB_RAM : origin = 0x040000, length = 0x000800 /* USB RAM */
FLASHB : origin = 0x3F0000, length = 0x004000 /* on-chip FLASH */
}
/* Allocate sections to memory blocks.
Note:
codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code
execution when booting to flash
ramfuncs user defined section to store functions that will be copied from Flash into RAM
*/
SECTIONS
{
GROUP {
/* Placement instructions for a linker generated CRC table data object */
.TI.crctab
/* Tell the linker to generate a single CRC table with a separate record for each output section */
.scn_1: { Example_2806xLEDBlink.obj(.text) } crc_table(_sboot_crc_table, algorithm = CRC16_ALT)
} > CRC_TABLE, PAGE = 0
/* Allocate program areas: */
.cinit : > FLASHH, PAGE = 0
.pinit : > FLASHH, PAGE = 0
.text : > FLASHH, PAGE = 0
codestart : > BEGIN, PAGE = 0
ramfuncs : LOAD = FLASHH,
RUN = RAML0,
LOAD_START(_RamfuncsLoadStart),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
LOAD_SIZE(_RamfuncsLoadSize),
PAGE = 0
csmpasswds : > CSM_PWL_P0, PAGE = 0
csm_rsvd : > CSM_RSVD, PAGE = 0
/* Allocate uninitialized data sections: */
.stack : > RAMM0, PAGE = 1
.ebss : > RAML4, PAGE = 1
.esysmem : > RAML2, PAGE = 1
.cio : > RAML5, PAGE = 1
/* Initialized sections to go in Flash */
/* For SDFlash to program these, they must be allocated to page 0 */
.econst : > FLASHH, PAGE = 0
.switch : > FLASHH, PAGE = 0
/* Allocate IQ math areas: */
IQmath : > FLASHH, PAGE = 0 /* Math Code */
IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD
/* Allocate FPU math areas: */
FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD
DMARAML5 : > RAML5, PAGE = 1
DMARAML6 : > RAML6, PAGE = 1
DMARAML7 : > RAML7, PAGE = 1
DMARAML8 : > RAML8, PAGE = 1
/* .reset is a standard section used by the compiler. It contains the */
/* the address of the start of _c_int00 for C Code. /*
/* When using the boot ROM this section and the CPU vector */
/* table is not needed. Thus the default type is set here to */
/* DSECT */
.reset : > RESET, PAGE = 0, TYPE = DSECT
vectors : > VECTORS, PAGE = 0, TYPE = DSECT
}
