This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

CCS: TMS570LC3137 - Question about Sci with DMA act



Tool/software: Code Composer Studio

I want to use DMA in SCI communication. And I make the code based on this link(https://e2e.ti.com/support/microcontrollers/hercules/f/312/t/807027?tisearch=e2e-sitesearch&keymatch=tms570ls3137%20sci%20with%20dma%20transfer )

I have some question about using DMA.

1. About trigger

  - Hardware Trigger : This trigger automatically, when DMA is enabled or SADD is set?

  - Software Trigger : I want to know this action. And it is possible to control the trigger timing when i want ?

2. DMA enable/disable Each channel.

  - I want to use just one channel(receive sci/transfer sci) . I want to know it is possible to use DMA as follows.

(1) Receive state : enable DMA receive sci / disable DMA transfer sci

(2) Transfer state : disable DMA receive sci / enable DMA transfer sci

 

Regards,

Minwoo

  • 1. About trigger

      - Hardware Trigger : This trigger automatically, when DMA is enabled or SADD is set?

    QJ> Yes, DMA module is enable, and SCI DMA functionality is enabled too (SET TX DMA, and SET RX DMA)

      - Software Trigger : I want to know this action. And it is possible to control the trigger timing when i want ?

    QJ>DMA supports both HW request and SW request. The transfer will be triggered by writing to SW Channel Enable Set and Status Register. You can enable this bit whenever you want.

     

    2. DMA enable/disable Each channel.

      - I want to use just one channel(receive sci/transfer sci) . I want to know it is possible to use DMA as follows.

    (1) Receive state : enable DMA receive sci / disable DMA transfer sci

    (2) Transfer state : disable DMA receive sci / enable DMA transfer sci

    QJ>Yes, you can use one channel for both TX and RX. But you need reconfig the packets and request line mapping. I'd like to use one channel for TX and another channel for RX.

  • Thanks for answer. QJ Wang, but I need some more detailed explanation.

    About trigger

     - Hardware trigger : In Tansmit state, If i set that DMA module is enable, and SCI DMA functionality is enabled. the data size is 100 byte.

       -> After send 100byte, Hardware trigger send packet start again automatically? (If dma is enabled, the data send is occurred repeatly with no delay)

    - Software Trigger : In Tansmit state, When i set SW Channel Enable Set and Status Register. Then, the data is transmitted one packet and stopped sending one packet? and SW Channel Enable Set and Status Register set as Zero(initialization value). If i want to trasmit again, I set SW Channel Enable Set and Status Register ?

  • Hello Minwoo,

    The hardware request can trigger either a frame or a block transfer depending on your setting of TTYPE bit in CHCTRL register.

    I assume that in your settings the element size is 1 byte and frame size is 100 elements, and block size is 20 frames. If you use frame transfer, after 1 frame (100 bytes) is transferred, the DMA request (HW or SW) is required to start the next  frame (100 bytes) transfer. It won't star automatically.

    But if you use block transfer, the 2nd frame will be transferred automatically after the 1st frame is transferred. The DMA request (HW or SW) is not required.

  • Hello QJ Wang,

    I understand your explain. I use the TTYPE as Block transfer now. I want to know when the next block is started in Hardware/Software Trigger.

    Regards,

    Minwoo

  • Hi Minwoo,

    Normally I use frame transfer for SCI DMA, and 1 frame consists of 1 element which is 1 byte if non-buffer mode is used. The TX/RX DMA request is generated at the moment the TXRDY/RXRDY bit is set.

    When the data in SCITD register has been moved to SCIXSHF register, the TXRDY bit is set and TX DMA request is generated, then next DMA transaction is triggered.

    When SCI transfers a received data from SCIRXSHF register to SCIRD, the RXRDY bit is set and the RX DMA request is generated, then the next DMA RX transaction is triggered.