CCS/TMS320C6655: How do i use CIC ? I want to link MCBSP's RINT with CPU interrupt.

Hi Masatoshi,

The most detailed tutorial on CIC is the following wiki:
 

Have you checked it?
Best Regards,
Yordan

Here is the correct link to Interrupt configuration using CIC provided on the wikis:

http://processors.wiki.ti.com/index.php/Configuring_Interrupts_on_Keystone_Devices

There is an example provided in section 3.1.3 and 3.2.4. 

Specifically for McBSP reference , you can refer to our McBSP driver and example in Processor SDK RTOS C665x but I suspect the driver uses DMA interrupt setup to move data from MCBSP FIFO to RX buffer to generate the interrupt.

HEre is an example of UART Interrrupt connection to CPU interrupts using CIC  for reference on C66x:

void KeyStone_UART_Interrupts_Init(Bool bRxIntEnable, Bool bEDMAInterruptEnable)
{
	if(C6670_EVM==gDSP_board_type
		||DUAL_NYQUIST_EVM==gDSP_board_type
		||TCI6614_EVM==gDSP_board_type)
	{	
		uiCIC_out_num= 64;//CIC out 64 is INTC input 22
	}
	else if(C6678_EVM==gDSP_board_type)
	{	
		uiCIC_out_num= 33;//in C6678, CIC out 33 is also INTC input 22
	}
	else
	{
		puts("Unknown DSP board type!");
		return;
	}	

	if(DNUM<4) //for core 0, 1, 2, 3
		CIC_Regs= gpCIC0_regs;
	else
		CIC_Regs= gpCIC1_regs;
    
	/* Disable Global host interrupts. */
	CIC_Regs->GLOBAL_ENABLE_HINT_REG= 0;

	/* Configure no nesting support in the CPINTC Module. */
	CIC_Regs->CONTROL_REG= ((CIC_Regs->CONTROL_REG&
		~CSL_CPINTC_CONTROL_REG_NEST_MODE_MASK)|
		(CPINTC_NO_NESTING<<CSL_CPINTC_CONTROL_REG_NEST_MODE_SHIFT));

	/*map UART ERR INT, RX EVT, and EDMA CC2 GINT to CIC out*/
	KeyStone_CIC_event_map(CIC_Regs, CSL_INTC0_UARTINT, uiCIC_out_num);
	KeyStone_CIC_event_map(CIC_Regs, CSL_INTC0_URXEVT, uiCIC_out_num+1);
#ifdef CSL_INTC0_UARTINT1
	KeyStone_CIC_event_map(CIC_Regs, CSL_INTC0_UARTINT1, uiCIC_out_num);
	KeyStone_CIC_event_map(CIC_Regs, CSL_INTC0_URXEVT1, uiCIC_out_num+1);
#endif
	KeyStone_CIC_event_map(CIC_Regs, CSL_INTC0_CPU_3_2_EDMACC_GINT, uiCIC_out_num+2);

	/* Enable Global host interrupts. */
	CIC_Regs->GLOBAL_ENABLE_HINT_REG= 1;

	/* map UART ERR interrupt to INT4 */
	/* map UART RX interrupt to INT5 */
	/* map EDMA GINT to INT6 */
#ifdef CSL_GEM_CIC0_OUT_64_PLUS_10_MUL_N 	//for C6670, TCI6614
	gpCGEM_regs->INTMUX1 = 
		(CSL_GEM_CIC0_OUT_64_PLUS_10_MUL_N<<CSL_CGEM_INTMUX1_INTSEL4_SHIFT)|\
		(CSL_GEM_CIC0_OUT_65_PLUS_10_MUL_N<<CSL_CGEM_INTMUX1_INTSEL5_SHIFT)|\
		(CSL_GEM_CIC0_OUT_66_PLUS_10_MUL_N<<CSL_CGEM_INTMUX1_INTSEL6_SHIFT);
#else  //for C6678
	gpCGEM_regs->INTMUX1 = 
		(CSL_GEM_INTC0_OUT_33_PLUS_11_MUL_N_OR_INTC0_OUT_33_PLUS_11_MUL_N_MINUS_4<<CSL_CGEM_INTMUX1_INTSEL4_SHIFT)|\
		(CSL_GEM_INTC0_OUT_34_PLUS_11_MUL_N_OR_INTC0_OUT_34_PLUS_11_MUL_N_MINUS_4<<CSL_CGEM_INTMUX1_INTSEL5_SHIFT)|\
		(CSL_GEM_INTC0_OUT_35_PLUS_11_MUL_N_OR_INTC0_OUT_35_PLUS_11_MUL_N_MINUS_4<<CSL_CGEM_INTMUX1_INTSEL6_SHIFT);
#endif
	/* enable INT4, 5, 6 */
	CPU_interrupt_enable((1<<4)|(bRxIntEnable<<5)|(bEDMAInterruptEnable<<6));
}

Please let us know if you have any further questions regarding this issue.

Regards,

Rahul