Part Number: MSP432P401R
Tool/software: Code Composer Studio
Hi,
There are two troubles I met these days.
One is MCLK and the other is UART communication.
I download the same code on both EVM and the PCB we created.
EVM can work but PCB can't.
1. I used 22pf capacitance and 48MHz as high frequency of MSP432 HFXIN and HFXOUT.
With the same control code, MCLK can be set as 48MHz on the MSP432P401R-EVM but it can't on my PCB (Only 15MHz and not stable).
PCB created reference is the datasheet of the EVM, check the schematic with the following file.
I change the MCLK source to DCO and my PCB can be set as 48MHz, so I use DCO output as my MCLK source now.
How can I solve the problem to make the MCLK is 48MHz with high frequency crystal?
2. I used MCLK(48MHz) as the EUSCI_A0 source, UART format is 9600-N-1 8 bits data.
It can work on EVM but can't on my PCB.
MSP432 can not receive the UART data. (I use break point to check, it did not enter EUSCIA0_IRQHandler ISR)
I also change my code to transmit data via UART, I am not able to receive the data from MSP432.
The same code can operate on the EVM board.
I have check the MCLK is exactly 48MHz.
The RXD and TXD pins are connected correctly from the connector and the chip.
Are there any setting that I missed?
Btw, Why do I need to use a delay for 700ms between transmit previous and the next data or it will miss the data?
It don't need in MSP430, and I have ask before but I didn't get the answer.
The post has disappeared since TI employee think it is resolve but it actually don't.
Schematic file:
Code:
//***MCLK setting as HF****
void Set_System_clk(void)//chip=MSP432P401Y
{
unsigned int currentPowerState;
/* NOTE: This example assumes the default power state is AM0_LDO.
* Refer to msp432p401x_pcm_0x code examples for more complete PCM operations
* to exercise various power state transitions between active modes.
*/
/* Step 1: Transition to VCORE Level 1: AM0_LDO --> AM1_LDO */
/* Get current power state, if it's not AM0_LDO, error out */
currentPowerState = PCM->CTL0 & PCM_CTL0_CPM_MASK;
if (currentPowerState != PCM_CTL0_CPM_0)
while(1);
while ((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_1;
while ((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
if (PCM->IFG & PCM_IFG_AM_INVALID_TR_IFG)
while(1); // Error if transition was not successful
if ((PCM->CTL0 & PCM_CTL0_CPM_MASK) != PCM_CTL0_CPM_1)
while(1); // Error if device is not in AM1_LDO mode
/* Step 2: Configure Flash wait-state to 1 for both banks 0 & 1 */
FLCTL->BANK0_RDCTL = (FLCTL->BANK0_RDCTL & ~(FLCTL_BANK0_RDCTL_WAIT_MASK)) | FLCTL_BANK0_RDCTL_WAIT_1;
FLCTL->BANK1_RDCTL = (FLCTL->BANK0_RDCTL & ~(FLCTL_BANK1_RDCTL_WAIT_MASK)) | FLCTL_BANK1_RDCTL_WAIT_1;
/* Step 3: Configure HFXT to use 48MHz crystal, source to MCLK & HSMCLK*/
PJSEL0 |= BIT2 | BIT3; // Configure PJ.2/3 for HFXT function
PJSEL1 &= ~(BIT2 | BIT3);
CS->KEY = CS_KEY_VAL ; // Unlock CS module for register access
CS->CTL2 |= CS_CTL2_HFXT_EN | CS_CTL2_HFXTFREQ_6 | CS_CTL2_HFXTDRIVE;
while(CS->IFG & CS_IFG_HFXTIFG)
CS->CLRIFG |= CS_CLRIFG_CLR_HFXTIFG;
/* Select MCLK & HSMCLK = HFXT, no divider */
CS->CTL1 = CS->CTL1 & ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK | CS_CTL1_SELS_MASK | CS_CTL1_DIVHS_MASK) | CS_CTL1_SELM__HFXTCLK | CS_CTL1_SELS__HFXTCLK;
CS->KEY = 0; // Lock CS module from unintended accesses
/* Step 4: Output MCLK to port pin to demonstrate 48MHz operation */
P4DIR |= BIT3;// Output MCLK
P4SEL0 |=BIT3;
//P4SEL1 &= ~BIT3;//default is 0
P4DIR |= BIT2;// Output ACLK
P4SEL0 |=BIT2;
//P4SEL1 &= ~BIT2;//default is 0
}
//***MCLK set as DCO***
void Set_System_clk(void)//chip=MSP432P401Y
{
unsigned int currentPowerState;
// NOTE: This example assumes the default power state is AM_LDO_VCORE0.
// Step 1: Transition to VCORE Level 1: AM_LDO_VCORE0 --> AM_LDO_VCORE1
// Get current power state, if it's not AM_LDO_VCORE0, error out
currentPowerState = PCM->CTL0 & PCM_CTL0_CPM_MASK;
// Skip the power mode config if PCM is already in AM1_DCDC
if (currentPowerState != PCM_CTL0_CPM_5)
{
if (currentPowerState != PCM_CTL0_CPM_0)
while(1);
while ((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_1;
while ((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
if (PCM->IFG & PCM_IFG_AM_INVALID_TR_IFG)
while(1); // Error if transition was not successful
if ((PCM->CTL0 & PCM_CTL0_CPM_MASK) != PCM_CTL0_CPM_1)
while(1); // Error if device is not in AM1_LDO mode
// Step 2: Transition from AM1_LDO to AM1_DCDC
while ((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_5;
while ((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
if (PCM->IFG & PCM_IFG_AM_INVALID_TR_IFG)
while(1); // Error if transition was not successful
if ((PCM->CTL0 & PCM_CTL0_CPM_MASK) != PCM_CTL0_CPM_5 )
while(1); // Error if device is not in AM_DCDC_VCORE1 mode
}
// Step 3: Configure Flash wait-state to 1 for both banks 0 & 1
FLCTL->BANK0_RDCTL = (FLCTL->BANK0_RDCTL & ~(FLCTL_BANK0_RDCTL_WAIT_MASK)) | FLCTL_BANK0_RDCTL_WAIT_1;
FLCTL->BANK1_RDCTL = (FLCTL->BANK0_RDCTL & ~(FLCTL_BANK0_RDCTL_WAIT_MASK)) | FLCTL_BANK1_RDCTL_WAIT_1;
// Step 4&5: Configure DCO to 48MHz, ensure MCLK uses DCO as source
CS->KEY = CS_KEY_VAL ; // Unlock CS module for register access
CS->CTL0 = 0; // Reset tuning parameters
CS->CTL0 = CS_CTL0_DCORSEL_5; // Set DCO to 48MHz
// Select MCLK = DCO, no divider
CS->CTL1 = (CS->CTL1 & ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK)) | CS_CTL1_SELM_3;
CS->KEY = 0; // Lock CS module from unintended accesses
// Output MCLK and ACLK to port pin to demonstrate 48MHz operation
P4DIR |= BIT3;// Output MCLK
P4SEL0 |=BIT3;
//P4SEL1 &= ~BIT3;//default is 0
P4DIR |= BIT2;// Output ACLK
P4SEL0 |=BIT2;
//P4SEL1 &= ~BIT2;//default is 0
}
//***UART operation***
void TX_Data_Operation
{
//****************
//* TX Operation *
//****************
while(UART_State<UART_Data[0])
{
EUSCI_A0->TXBUF = UART_Data[UART_State++];
Delay_micorsec(700);
}
UART_State=0;
}
void UART_Set(void)
{
P1SEL0 |= (RXD + TXD);
P1SEL1 &= ~(RXD + TXD);
EUSCI_A0->CTLW0 |= EUSCI_A_CTLW0_SWRST; // Put eUSCI in reset
EUSCI_A0->CTLW0 = EUSCI_A_CTLW0_SWRST | // Remain eUSCI in reset
EUSCI_B_CTLW0_SSEL__SMCLK; // Configure eUSCI clock source for SMCLK
EUSCI_A0->BRW = 312;
EUSCI_A0->MCTLW = (8 << EUSCI_A_MCTLW_BRF_OFS) | EUSCI_A_MCTLW_OS16;
EUSCI_A0->CTLW0 &= ~EUSCI_A_CTLW0_SWRST; // Initialize eUSCI
EUSCI_A0->IFG &= ~EUSCI_A_IFG_RXIFG; // Clear eUSCI RX interrupt flag
EUSCI_A0->IE |= EUSCI_A_IE_RXIE; // Enable USCI_A0 RX interrupt
NVIC->ISER[0] = 1 << ((EUSCIA0_IRQn) & 31); // Enable eUSCIA0 interrupt in NVIC module
__enable_irq(); // Enable global interrupt
}
void EUSCIA0_IRQHandler(void)
{
UART_Data[(UART_State & UART_State_Count)] = EUSCI_A0->RXBUF;
UART_State++;
if((UART_State & UART_State_Count) >= UART_Data[0])
UART_State = UART_State_Finish;
}
BR,
Yu-Chuan, Chen
