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CCS/TMS320F28388D: Device is getting random reset and after reset CPU stuck at reset vector

Vivek Singh
Guru** 115881 points
Part Number: TMS320F28388D


Tool/software: Code Composer Studio

I am facing this strange reset issue on my device. After I run the code, it hangs and when I pause, I see PC points to reset vector. It it's normal reset then CPU should go through the reset cycle and start from reset vector and keep executing the BOOT code but in this case it get stuck at reset vector and does not execute anything as if a debugger reset has been issued and CPU halts at reset vector. My question is -

  • Is there any way CCS can forces the reset to CPU ? E.g. there is bus hang condition which can cause CCS to force debug reset?
  • If yes, can I disable this feature in CCS?

Regards,

Vivek Singh

  • 0
    TI__Guru**** 171309 points

    Hi Vivek, 

    Vivek Singh said:
    After I run the code, it hangs and when I pause, I see PC points to reset vector. (...) but in this case it get stuck at reset vector and does not execute anything as if a debugger reset has been issued and CPU halts at reset vector.

    I have seen this happen when the Deubg Probe still believes it is fully connected to the target core but in fact the core/device is either running freely, the clock domain is powered down or is in low power mode - unfortunately the Debug Probe can only have so much awareness about the hardware status.

    Given this device seems to have an ICEPICK, what does the Core Status show? Check section 7.5.7 of the CCS User's Guide:

    https://software-dl.ti.com/ccs/esd/documents/users_guide/index.html

    CCS can issue reset commands via JTAG or via the nRESET (System Reset) pin. The latter requires HW to be in place, but the "soft" reset modes may be able to restore or at least give you additional indication of what may be going on - I have seen both scenarios: either the Debug Probe regains control over the device or reports the device never came back from reset.

    If the Debug Probe detects a core hung, it will always prompt for the action if it feels it can restore the connection. For that particular condition, check the "Device Hung" section of the Debugging JTAG page at: 

    https://software-dl.ti.com/ccs/esd/documents/ccs_debugging_jtag_connectivity_issues.html 

    Hope this helps,

    Rafael

  • 0 in reply to desouza
    TI__Guru** 115881 points

    Hi Rafael,

    Thank you for the quick response.

    CCS can issue reset commands via JTAG or via the nRESET (System Reset) pin. The latter requires HW to be in place, but the "soft" reset modes may be able to restore or at least give you additional indication of what may be going on - I have seen both scenarios: either the Debug Probe regains control over the device or reports the device never came back from reset.

    How the CCS issues the reset command via JTAG ? Is there a way to disable this feature in CCS. Also in what circumstances CCS issues this reset. In our case there is possibility that system clock is turned off for some time (30-40 cycle) during application run. Can that trigger CCS to issue reset (via JTAG or nRESET) ?

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    TI__Guru**** 171309 points

    Vivek,

    Vivek Singh said:
    How the CCS issues the reset command via JTAG ?

    One of the registers accessed by the Debug Probe has some control over the reset functions of the device. I am not entirely sure how this is mapped to the CCS GUI, though. 

    Vivek Singh said:
    Is there a way to disable this feature in CCS. Also in what circumstances CCS issues this reset.

    As long as you don't explicitly issue this command, CCS by default does not reset the target. Keep in mind that the project or the Debug Configuration may have the options "Reset the target on a connect", "Reset the target on a program load or restart" enabled. Also, GEL files may issue reset commands. Check section 7.2.2 of the CCS User's Guide (menu Help --> Contents) for details about the Debug Configuration options. 

    Vivek Singh said:
    In our case there is possibility that system clock is turned off for some time (30-40 cycle) during application run. Can that trigger CCS to issue reset (via JTAG or nRESET) ?

    I think this will simply inform the Debug Probe the device/core is in power down mode and a reset is not automatically triggered. In this case, you can put the core to "Free Run" (Ctrl+F8) and it should coast through these power transitions without a glitch. 

    Hope this helps,

    Rafael