Tool/software: TI C/C++ Compiler
Hello All,
For TI-CGT-ARM-V18.12.1:
1) In AWR1843 device, the core cortex r4f has 3 memories (ROM, TCMA & TCMB), after building an application for that core, using a linker script which has no any information about sections allocation, as I wanted to watch its default sections allocation. I found that all section (.txt, .data, .bss & etc.) are allocated within the ROM range which hosts only the bootloader as mentioned in the technical user manual.
Through the linker script & the map file, am I dealing with real physical addresses or something else?
2) Through the linker there are two attributes (Load & Run addresses), used in section directive:
- Does "load address" deal with the Serial Data Flash (SDF) ?
- Does "run address" deal with TCMA & TCMB ?
3) When I flash a certain image, is it flashed on ROM/TCMA/TCMB/SDF ?
4) I have read in the manual that memory initialization could be done by hardware using (MEMINITSTART & MEMINITDONE) registers:
- Nothing happens after writing values to those registers, even their own values aren't changed.
The linker script:
The output map file:
Cortex R4F memories' ranges:
Thanks in advance.