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Original question:

AM5728: QSPI flash access in baremetal

CCS/66AK2G12: how to access BAR( Bank Address Register) in Qspi flash memory - S25FL-S

selvamuthukumaran g
Intellectual 445 points
Part Number: 66AK2G12

Tool/software: Code Composer Studio

hi,

Processor: - evmk2g

SDK:- pdk_k2g_1_10_14

CCS: - v.9

I am trying to flash QSPI flash memory using J-tag I am loading the MLO and app from SD card and flashing it into the QSPI flash memory.

MLO - 0x0, 0x40000 OFFSET address.

app - 0x80000 OFFSET address.

I can able to flash the MLO of size 129KB in both the offset and app file size of below 16MB and it is working fine.

when I tried to flash app file size of above 16MB it is erasing MLO sector data and it is not working, from the device datasheet I have understood that by default the device will support only 3byte addressing (16MB) 

to enable more than that I need to enable BAR bank address register BAR1[7] = 1.

can anyone tell how to configure this in my Evmk2g

it is blocker for my project to proceed so please respond me ASAP

thanks,

Selvamuthukumaran. G

  • 0
    TI__Guru** 116170 points

    Selvamuthukumaran,

    It appears that the flashwriter source included as part of our boot utilities does not currently support 4 byte addressing mode but if you look at the flash driver that is part of our QSPI flash offering, we provide a function called S25FLFlash_Enable4ByteAddrMode that will setup the flash in 4 byte addressing mode to allow you to access the higher 16 MB of the flash. 

    If you do incorporate the change in the flash writer, the other change that will be required will require you to enable the Read and write commands to flash with 4 byte addressing so the buffer size will need to change based on whether the driver is in 3 byte address mode (default) or changed to 4 byte addressing. Please refer to the files S25FL.c in the QSPI driver test located at:

    C:\ti\K2G_PRSDK61\pdk_k2g_1_0_15\packages\ti\drv\spi\test\qspi_flash\src\Flash_S25FL

    Look for the flag enable4ByteMode and enable4ByteMode in the code to understand the implementation to support 4 byte addressing.

    Regards,

    Rahul

  • 0 in reply to Rahul Prabhu
    Intellectual 445 points

    hi,

    we are using QSPI_BasicExample_evmK2G_armExampleProject for flashing the QSPI. in this we are using the API's like Board_flashopen, Board_flashRead please tell us the steps to enable 4byte mode addressing for this project.

  • 0 in reply to selvamuthukumaran g
    Intellectual 445 points

    hi,

    we are using QSPI_BasicExample_evmK2G_armExampleProject for flashing the QSPI. in this we are using the API's like Board_flashopen, Board_flashRead please tell us the steps to enable 4byte mode addressing for this project.

  • 0 in reply to Rahul Prabhu
    Intellectual 445 points

    hi,

    we are using QSPI_BasicExample_evmK2G_armExampleProject for flashing the QSPI. in this we are using the API's like Board_flashopen, Board_flashRead please tell us the steps to enable 4byte mode addressing for this project.

  • 0 in reply to selvamuthukumaran g
    TI__Guru** 116170 points

    As I indicated in my earlier post, it appears that the Board_flashread API doesn`t seem to have this feature implemented. The driver developer has provided the QSPI flash driver test code for demonstrating the access > 16 MB for AM57x devices for reference.

    https://git.ti.com/cgit/keystone-rtos/spi-lld/commit?id=9187fce8a1699540dec40a436f00b2f88c7f645e&dt=2

    K2G platform is also using the spansion flash S25FL as in case of AM57xx so the same flash driver API could be used in your K2G based code. We have have filed a bug that the K2G QSPI flash test doesn`t have this coverage. Let us know if the flash driver reference doesn`t suffice and we will try see if this can be addressed in the board library.

    The other option is to optimize your boot image so that it can fit in the 16 MB (3 byte addressing range). Can you indicate how big is your app image ? Have you removed stack and heaps from the image that adds a region of zeros that is not required to be loaded at the time of boot.

    http://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/index_Foundational_Components.html#usage-notes

    Regards,

    Rahul

     

  • 0 in reply to Rahul Prabhu
    Intellectual 565 points

    Hi,

    Im replying on behalf of selva.

    We tried to intergrate the changes corresponding to enable 4 byte addressing in C:\ti\pdk_k2g_1_0_14\packages\ti\board\src\flash\nor\qspi\nor_qspi.c. It seems like it doesn't have any effect.

    Whether are we making our changes in correct file for K2G? After making our changes in C:\ti\pdk_k2g_1_0_14\packages\ti\board\src\flash\nor\qspi\nor_qspi.c , is there any specific steps to compile that driver? Because we are just compiling our project, is that enough?

  • 0 in reply to sudhanthiradasan R
    Intellectual 565 points

    Hi Rahul Prabhu,

    The changes in https://git.ti.com/cgit/keystone-rtos/spi-lld/commit?id=9187fce8a1699540dec40a436f00b2f88c7f645e&dt=2 will not work for S25FL512S.

    For S25FL512S, we just have to enable EXT_ADDRESS_ENABLE in C:\ti\pdk_k2g_1_0_14\packages\ti\board\src\flash\nor\device\s25fl512s.h file.

    We have enabled it and compiled board libraries but it is not working.

    Once we have enable EXT_ADDRESS_ENABLE, flash will expect 32bit address. I have a doubt whether 32 bit address is sent from K2G device, whether such thing is taken care in qspi driver of K2G ?

    If not how to enable it?

    Can anyone help us from qspi driver team?

  • 0 in reply to sudhanthiradasan R
    TI__Guru** 116170 points

    The SPI driver only helps in read and writer using SPI and QSPI IP on the SOC. The three byte address of 4 byte address needs to be handled by the flash driver code that you are using (in your case board_flash driver). You will need to update the Board_flash driver to support the 4 byte addressing mode and have a flag for this driver to known when the flash is in three byte address mode or four byte address mode.

    The header change is not the one that is critical, the need to use 4 byte address length and a different read/write command during the 4 byte operation is what is critical. That is why I referred you to the S25FL.c implementation. I have attached the relevant code so we are on the same page:

    The Board_flash driver doesn`t support this switch to 32 bit addressing and only calls into the default read command and address approach. I have added the feature request which you can track using the bug ID. PRSDK-8089

    Regards,

    Rahul