CCS/TMS320F28379D: TMS320F28379D

Richard,

Sorry for my late reply, but I tried in all different ways to understand your reply. Could you please explain how my CMPA value is greater than the set value of timebase period. I initialized 

IntCount = 0;

but I am not getting any results.  

Thank you for your reply

Bighnaraj Panda

Richard,

I initialized IntCount as

__interrupt void epwm1_isr(void)
{
interrupt_count++;
unsigned long IntCount = 0;

....

and also inside the definition of EPwm 

void InitEPwm1Example()
{
unsigned long IntCount = 0;

...

But now I am now getting a straight line. As I think it is not getting compared so could you please elaborate on why it is not getting compared. 

Thank you

Bighnaraj Panda

Bighnaraj,

The only reason you're getting interrupts now is you've initialized IntCount inside Pwm1Example() where it's first used.  However, when you initialize it again as a local variable inside the ISR it's always zero every the interrupt is triggered and you always access the first element in your sine array. IntCount has to be a global variable, not a local variable.

I recommend you remove these two local declarations, go back to your original code at the top of this thread, and just initialize IntCount in line 18.  I have that running on my machine.

Regards,

Richard

Richard,

 Yes, I did it accordingly but I am getting a constant output.

void InitEPwm1Example()
{
unsigned long IntCount = 0;
//
// Setup TBCLK
//

EPwm1Regs.TBPRD = EPWM1_TIMER_TBPRD; // Set timer period 801 TBCLKs
EPwm1Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter

...

void InitEPwm2Example()
{
unsigned long IntCount = 0;
//
// Setup TBCLK
//
EPwm2Regs.TBPRD = EPWM2_TIMER_TBPRD; // Set timer period 801 TBCLKs
EPwm2Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm2Regs.TBCTR = 0x0000; // Clear counter

...

void InitEPwm3Example()
{
unsigned long IntCount = 0;
//
// Setup TBCLK
//
EPwm3Regs.TBPRD = EPWM3_TIMER_TBPRD; // Set timer period 801 TBCLKs
EPwm3Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm3Regs.TBCTR = 0x0000; // Clear counter

...

Have I changed it correctly.

Thank you

Bighnaraj Panda

You should be getting interrupts now, but it would be cleaner to get rid of these local variables and just do what I said - i.e. have one global IntCount variable which is initialized in line 18.

If you place a break-point on the first line of each ISR your should be able to step through each one - is that what happens?

Can you explain what you mean by constant output" please? 

Thanks.

Regards,

Richard

Richard,

Yes that also I tried I made the global variable also 

int interrupt_count = 1;
unsigned long IntCount=0;

Thank you

Bighnaraj Panda

Bighnaraj,

OK thanks.  You shouldn't need the local variable "IntCount" anwhere.

I see the 'scope trace, but what is it?  PWM output?

Here's the thing: I think this is a PWM output and what you mean to do is modulate the PWM duty cycle with the sine table, but nowhere in your code do you write to a PWM compare register inside an ISR, so I'm not sure what you expect to see.  Can you elaborate please?

Regards,

Richard 

Richard,

Yes it is the output across EPWM1. I think I have compared it with the compare register inside the definition of InitEPwm1Example as follows

void InitEPwm1Example()
{
//unsigned long IntCount = 0;
//
// Setup TBCLK
//

EPwm1Regs.TBPRD = EPWM1_TIMER_TBPRD; // Set timer period 801 TBCLKs
EPwm1Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter

//
// Set Compare values
//
EPwm1Regs.CMPA.bit.CMPA = SineTable[IntCount]; // Set compare A value
EPwm1Regs.CMPB.bit.CMPB = SineTable[IntCount]; // Set Compare B value

Could you suggest what changes I need to make inside the ISR

Thank you

Bighnaraj Panda

Bighnaraj,

You have initialized the duty cycle, but if you want it to change as the program runs you're going to have to write to it inside your ISR.  Copy the two lines above which set the compare values to the end of your PWM1 ISR. 

Regards,

Richard

Richard,

Yes I did accordingly but still, the output is constant

__interrupt void epwm1_isr(void)
{
interrupt_count++;

// Generate 2nd interrupt when Counter down count = CMPB
if(interrupt_count == 2)
{
GpioDataRegs.GPBDAT.bit.GPIO63 = 1; //set GPIO-63 high
// GpioDataRegs.GPBSET.bit.GPIO63 = 1; //set GPIO-63 high
// GpioDataRegs.GPADAT.bit.GPIO14 = 1; //set GPIO-14 high
// GpioDataRegs.GPASET.bit.GPIO14 = 1; //set GPIO-14 high
EPwm1Regs.ETSEL.bit.INTSEL = 7;
}

// After generating interrupt when counter down count = CMPB
// Reset the next interrupt to generate again when counter up count = CMPA
else
{
GpioDataRegs.GPBDAT.bit.GPIO63 = 0; //set GPIO-63 low
// GpioDataRegs.GPBCLEAR.bit.GPIO63 = 1; //set GPIO-63 low
// GpioDataRegs.GPADAT.bit.GPIO14 = 0; //set GPIO-14 low
// GpioDataRegs.GPACLEAR.bit.GPIO14 = 1; //set GPIO-14 low
EPwm1Regs.ETSEL.bit.INTSEL = 4;
interrupt_count = 1;
}

EPwm1Regs.ETCLR.bit.INT = 1;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
//if( IntCount < 100)
// {
// IntCount++;
//}
//else
// IntCount = 0;
EPwm1Regs.CMPA.bit.CMPA = SineTable[IntCount]; // Set compare A value
EPwm1Regs.CMPB.bit.CMPB = SineTable[IntCount];
}

Thank you

Bighnaraj Panda

Hi Bighnaraj,

This is going to get a little complicated. What you are doing is basically OK, but there are some things you need to change. First, let's try an experiment. Change the CMPA / CMPB settings to some fixed value below TBPRD. You'll need to do this both in your ISR and in the init routine. Use something like:

EPwm1Regs.CMPA.bit.CMPA = 0x200;
EPwm1Regs.CMPB.bit.CMPB = 0x300;

Now build and run the program. Do you see an output? I think you will see a fixed value different from before. Then, place a break point on the first line of the ePWM1 ISR and check that it triggers every time you run the program. Please let me know if it does this and what you find. Thanks.

Regards,

Richard

Richard,

I understand that if I will set 

EPwm1Regs.CMPA.bit.CMPA , value within the period TBPRD then I will get a square pulse response. But I cannot understand how to make the lookup table values of sine_table to be comparable with "EPwm1Regs.CMPA.bit.CMPA" registers. 

Thank you

Bighnaraj Panda

Bighnaraj,

Can you first confirm you are reaching the break point at the start of the PWM1 ISR repeatedly?  I think you should be.

Regards,

Richard

Richard,

             Yes this is the PWM output taken across EPWM1 (J4 Pin 40). I want to modulate the output PWM duty cycle by comparing it with sine wave. If you could suggest me how to modulate the duty cycle inside the ISR. By writing 

EPwm3Regs.CMPA.bit.CMPA = SineTable[IntCount];

I am trying to assign the current sine value to compare bit register so that a modulate PWM wave is produced.

Thank you

Bighnaraj Panda

Bighnaraj,

Please could you answer my question about triggering repeatedly on the PWM1 ISR?

Place a break point on the first line of epw1_isr and run the program.  Do you reach it?

Run the program again. Do you reach it again?

Until this is happening the look up table is irrelevant.

Regards,

Richard

Richard,

           I studied some of the example programs and one link about the sine lookup table. According to your suggestions, I tried to modify the duty ratio inside the ISR for the compare value set. Now i am getting square pulses of equal duty ratio. If you could suggest any modifications. Following are the modifications I have done

1.  
2. // epwm1_isr - EPWM1 ISR
3. //
4. __interrupt void epwm1_isr(void)
5. {
6.     interrupt_count++;
7.  
8.     // Generate 2nd interrupt when Counter down count = CMPB
9.     if(interrupt_count == 2)
10.         {
11.             GpioDataRegs.GPBDAT.bit.GPIO63 = 1; //set GPIO-63 high
12. //            GpioDataRegs.GPBSET.bit.GPIO63 = 1; //set GPIO-63 high
13. //            GpioDataRegs.GPADAT.bit.GPIO14 = 1; //set GPIO-14 high
14. //            GpioDataRegs.GPASET.bit.GPIO14 = 1; //set GPIO-14 high
15.             EPwm1Regs.ETSEL.bit.INTSEL = 7;
16.         }
17.  
18.     // After generating interrupt when counter down count = CMPB
19.     // Reset the next interrupt to generate again when counter up count = CMPA
20.     else
21.     {
22.         GpioDataRegs.GPBDAT.bit.GPIO63 = 0; //set GPIO-63 low
23. //            GpioDataRegs.GPBCLEAR.bit.GPIO63 = 1; //set GPIO-63 low
24. //            GpioDataRegs.GPADAT.bit.GPIO14 = 0; //set GPIO-14 low
25. //            GpioDataRegs.GPACLEAR.bit.GPIO14 = 1; //set GPIO-14 low
26.         EPwm1Regs.ETSEL.bit.INTSEL = 4;
27.         interrupt_count = 1;
28.     }
29.     if( IntCount < 100)
30.        {
31.          IntCount++;
32.       }
33.       else
34.         IntCount = 0;
35.     EPwm1Regs.CMPA.bit.CMPA = EPwm1Regs.TBPRD-SineTable[IntCount]/2;    // Set compare A value
36.       EPwm1Regs.CMPB.bit.CMPB = EPwm1Regs.TBPRD-SineTable[IntCount]/2;
37.  
38.       if( IntCount < 100)
39.          {
40.            IntCount++;
41.         }
42.         else
43.           IntCount = 0;
44.       EPwm1Regs.ETCLR.bit.INT = 1;
45.       PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
46.     //EPwm1Regs.CMPA.bit.CMPA = 0x200;
47.       //  EPwm1Regs.CMPB.bit.CMPB = 0x300;
48. }
49. __interrupt void epwm2_isr(void)
50. {
51. EPwm2Regs.CMPA.bit.CMPA = EPwm2Regs.TBPRD-SineTable[IntCount]/2;    // Set compare A value
52.     EPwm2Regs.CMPB.bit.CMPB = EPwm2Regs.TBPRD-SineTable[IntCount]/2;    // Set Compare B value
53.  
54.     if( IntCount < 100)
55.       {
56.        IntCount++;
57.      }
58.     else
59.       IntCount = 0;
60.  
61.     EPwm2Regs.ETCLR.bit.INT = 1;
62. PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
63. }
64. __interrupt void epwm3_isr(void)
65. {
66.     EPwm3Regs.CMPA.bit.CMPA = EPwm3Regs.TBPRD-SineTable[IntCount]/2;    // Set compare A value
67.             EPwm3Regs.CMPB.bit.CMPB = EPwm3Regs.TBPRD-SineTable[IntCount]/2;    // Set Compare B value
68.             if( IntCount < 100)
69.               {
70.                IntCount++;
71.            }
72.            else
73.             IntCount = 0;
74.     // Clear INT flag for this timer
75.     //
76.     EPwm3Regs.ETCLR.bit.INT = 1;
77.  
78.     //
79.     // Acknowledge this interrupt to receive more interrupts from group 3
80.     //
81.     PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
82. }
83. //
84. // InitEPwm1Example - Initialize EPWM1 configuration
85. //
86. void InitEPwm1Example()
87. {
88.     //unsigned long IntCount = 0;
89.     //
90.     // Setup TBCLK
91.     //
92.  
93.     EPwm1Regs.TBPRD = EPWM1_TIMER_TBPRD;       // Set timer period 801 TBCLKs
94.     EPwm1Regs.TBPHS.bit.TBPHS = 0x0000;        // Phase is 0
95.     EPwm1Regs.TBCTR = 0x0000;                  // Clear counter
96.  
97.     //
98.     // Set Compare values
99.     //
100.     EPwm1Regs.CMPA.bit.CMPA = EPwm1Regs.TBPRD/2; //SineTable[IntCount];    // Set compare A value
101.     EPwm1Regs.CMPB.bit.CMPB = EPwm1Regs.TBPRD/2; //SineTable[IntCount];    // Set Compare B value
102.     //EPwm1Regs.CMPA.bit.CMPA = 0x200;
103.       //      EPwm1Regs.CMPB.bit.CMPB = 0x300;
105. void InitEPwm2Example()
106. {
107.     //unsigned long IntCount = 0;
108.     //
109.     // Setup TBCLK
110.     //
111.     EPwm2Regs.TBPRD = EPWM2_TIMER_TBPRD;       // Set timer period 801 TBCLKs
112.     EPwm2Regs.TBPHS.bit.TBPHS = 0x0000;        // Phase is 0
113.     EPwm2Regs.TBCTR = 0x0000;                  // Clear counter
114.  
115.     //
116.     // Set Compare values
117.     //
118.     EPwm2Regs.CMPA.bit.CMPA = EPwm2Regs.TBPRD/2; //SineTable[IntCount];    // Set compare A value
119.     EPwm2Regs.CMPB.bit.CMPB = EPwm2Regs.TBPRD/2; //SineTable[IntCount];    // Set Compare B value
121. void InitEPwm3Example()
122. {
123.     //unsigned long IntCount = 0;
124.     //
125.     // Setup TBCLK
126.     //
127.     EPwm3Regs.TBPRD = EPWM3_TIMER_TBPRD;       // Set timer period 801 TBCLKs
128.     EPwm3Regs.TBPHS.bit.TBPHS = 0x0000;        // Phase is 0
129.     EPwm3Regs.TBCTR = 0x0000;                  // Clear counter
130.  
131.     //
132.     // Set Compare values
133.     //
134.     EPwm3Regs.CMPA.bit.CMPA = EPwm3Regs.TBPRD/2; //SineTable[IntCount];    // Set compare A value
135.     EPwm3Regs.CMPB.bit.CMPB = EPwm3Regs.TBPRD/2; //SineTable[IntCount];    // Set Compare B value
137.  

Thank you

Bighnaraj Panda

Richard,

             I put the breakpoint at 

    interrupt_count++;

and while I run the program then it is stoping. It is not reaching the breakpoint. Should I change the lookup table.

Thank you

Bighnaraj Panda

Bighnaraj,

There are two issues with your code. One of them involves the sine table, but before we get to that I need to be sure your code is repeatedly getting to those ISRs, otherwise there's no point.

Earlier I asked you to make some changes to your code to remove reads of the sine table and check the ISR entry. Look back at that post - it's the 5th one in this thread. Please remove those reads, run the test, and let me know if it works. Just forget the output for now, I only want to know if it's going into the ISRs. Thanks.

Regards,

Richard

Richard,

            I removed the read of sine_table[IntCount] inside the CMPA register but still the breakpoints at ISR is not updating the registers as the image attached

EPwm1Regs.CMPA.bit.CMPA = EPwm1Regs.TBPRD/2; //SineTable[IntCount]; // Set compare A value
EPwm1Regs.CMPB.bit.CMPB = EPwm1Regs.TBPRD/2; //SineTable[IntCount]; // Set Compare B value

Thank you

Bighnaraj Panda

Bighnaraj,

A lot of changes have been made to the code and I'm having a hard time keeping up, so I'd like to try this the other way around.  I have attached a C file which I think is close to what you have now.  I'd like you to replace the file you're working on with this one.

Then, build and load as usual, and place a break point on line 99 and run the program.  You should be hitting this break point each time you run.  Please confirm this happens.  Thanks.

Regards,

Richard

#include "F28x_Project.h"
//
// Defines
//
#define Sine_TABLE_LENGTH 100
#define EPWM1_TIMER_TBPRD  2500  // Period register
#define EPWM2_TIMER_TBPRD  2500
#define EPWM3_TIMER_TBPRD  2500

#pragma DATA_SECTION(SineTable,"SineTableSection")
uint32_t SineTable[Sine_TABLE_LENGTH]={
 0x00000000,0x41bc646b,0x423c5e7a,0x428d3f6d,0x42bc46b4,0x42eb421a,0x430d1754,0x432484b3,0x433be7b1,0x43533ed4,0x436a88a2,0x4380e1d2,0x438c7731,0x439803b2,0x43a3869d,0x43aeff36,0x43ba6cc3,0x43c5ce8e,0x43d123dd,0x43dc6bfa,0x43e7a62e,0x43f2d1c4,0x43fdee08,0x44047d23,0x4409fae6,0x440f6ff4,0x4414dbf5,0x441a3e91,0x441f9771,0x4424e640,0x442a2aa7,0x442f6451,0x443492ea,0x4439b61e,0x443ecd9a,0x4443d90c,0x4448d822,0x444dca8c,0x4452affa,0x4457881c,0x445c52a4,0x44610f46,0x4465bdb4,0x446a5da3,0x446eeec8,0x447370d5,0x4477e38e,0x447c469f,0x44804ce2,0x44826e5d,0x4484879c,0x4486987e,0x4488a0e3,0x448aa0a8,0x448c97ae,0x448e85d4,0x44906afd,0x44924709,0x449419d9,0x4495e352,0x4497a355,0x449959c6,0x449b068b,0x449ca987,0x449e42a1,0x449fd1be,0x44a156c5,0x44a2d19e,0x44a44231,0x44a5a867,0x44a70429,0x44a85561,0x44a99bf9,0x44aad7de,0x44ac08fb,0x44ad2f3d,0x44ae4a92,0x44af5ae7,0x44b0602b,0x44b15a4f,0x44b24941,0x44b32cf4,0x44b40558,0x44b4d260,0x44b593ff,0x44b64a29,0x44b6f4d3,0x44b793f1,0x44b82779,0x44b8af63,0x44b92ba6,0x44b99c39,0x44ba0116,0x44ba5a36,0x44baa794,0x44bae92b,
 0x44bb1ef7,0x44bb48f4,0x44bb6720,0x44bb7978,0x44bb7ffc};

/// CMPA and CMPB sum should be 2500 for 50% duty cycle
//
int interrupt_count = 1;
unsigned long IntCount = 0;

// Function Prototypes
void Gpio_setup (void);
void InitEPwm1Example(void);
void InitEPwm2Example(void);
void InitEPwm3Example(void);
__interrupt void epwm1_isr(void);
__interrupt void epwm2_isr(void);
__interrupt void epwm3_isr(void);
//
// Main
//
void main(void)
{
    InitSysCtrl();

    InitGpio();
    Gpio_setup ();

    CpuSysRegs.PCLKCR2.bit.EPWM1=1;
    CpuSysRegs.PCLKCR2.bit.EPWM2=1;
    CpuSysRegs.PCLKCR2.bit.EPWM3=1;

    InitEPwm1Gpio();
    InitEPwm2Gpio();
    InitEPwm3Gpio();

    DINT;

    InitPieCtrl();

    IER = 0x0000;
    IFR = 0x0000;

    InitPieVectTable();
//
    EALLOW; // This is needed to write to EALLOW protected registers
    PieVectTable.EPWM1_INT = &epwm1_isr;
    PieVectTable.EPWM2_INT = &epwm2_isr;
    PieVectTable.EPWM3_INT = &epwm3_isr;
    EDIS;   // This is needed to disable write to EALLOW protected registers

    EALLOW;
    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;
    EDIS;

    InitEPwm1Example();
    InitEPwm2Example();
    InitEPwm3Example();

    EALLOW;
    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;
    EDIS;

    IER |= M_INT3;

    PieCtrlRegs.PIEIER3.bit.INTx1 = 1;
    PieCtrlRegs.PIEIER3.bit.INTx2 = 1;
    PieCtrlRegs.PIEIER3.bit.INTx3 = 1;

//
// Enable global Interrupts and higher priority real-time debug events:
//
    EINT;  // Enable Global interrupt INTM
    ERTM;  // Enable Global realtime interrupt DBGM

//
// Step 5. IDLE loop. Just sit and loop forever (optional):

    while(1)
    {
    }
}

//
// epwm1_isr - EPWM1 ISR
//
// epwm1_isr - EPWM1 ISR
//
__interrupt void epwm1_isr(void)
{
    interrupt_count++;

    // Generate 2nd interrupt when Counter down count = CMPB
    if(interrupt_count == 2)
        {
            GpioDataRegs.GPBDAT.bit.GPIO63 = 1; //set GPIO-63 high
//            GpioDataRegs.GPBSET.bit.GPIO63 = 1; //set GPIO-63 high
//            GpioDataRegs.GPADAT.bit.GPIO14 = 1; //set GPIO-14 high
//            GpioDataRegs.GPASET.bit.GPIO14 = 1; //set GPIO-14 high
            EPwm1Regs.ETSEL.bit.INTSEL = 7;
        }

    // After generating interrupt when counter down count = CMPB
    // Reset the next interrupt to generate again when counter up count = CMPA
    else
    {
        GpioDataRegs.GPBDAT.bit.GPIO63 = 0; //set GPIO-63 low
//            GpioDataRegs.GPBCLEAR.bit.GPIO63 = 1; //set GPIO-63 low
//            GpioDataRegs.GPADAT.bit.GPIO14 = 0; //set GPIO-14 low
//            GpioDataRegs.GPACLEAR.bit.GPIO14 = 1; //set GPIO-14 low
        EPwm1Regs.ETSEL.bit.INTSEL = 4;
        interrupt_count = 1;
    }
    if( IntCount < 100)
       {
         IntCount++;
      }
      else
        IntCount = 0;
//    EPwm1Regs.CMPA.bit.CMPA = EPwm1Regs.TBPRD-SineTable[IntCount]/2;    // Set compare A value
//      EPwm1Regs.CMPB.bit.CMPB = EPwm1Regs.TBPRD-SineTable[IntCount]/2;
      EPwm1Regs.CMPA.bit.CMPA = EPwm1Regs.TBPRD/2; //SineTable[IntCount]; // Set compare A value
      EPwm1Regs.CMPB.bit.CMPB = EPwm1Regs.TBPRD/2; //SineTable[IntCount]; // Set Compare B value

      if( IntCount < 100)
         {
           IntCount++;
        }
        else
          IntCount = 0;
      EPwm1Regs.ETCLR.bit.INT = 1;
      PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
    //EPwm1Regs.CMPA.bit.CMPA = 0x200;
      //  EPwm1Regs.CMPB.bit.CMPB = 0x300;
}


__interrupt void epwm2_isr(void)
{
EPwm2Regs.CMPA.bit.CMPA = EPwm2Regs.TBPRD-SineTable[IntCount]/2;    // Set compare A value
    EPwm2Regs.CMPB.bit.CMPB = EPwm2Regs.TBPRD-SineTable[IntCount]/2;    // Set Compare B value

    if( IntCount < 100)
      {
       IntCount++;
     }
    else
      IntCount = 0;

    EPwm2Regs.ETCLR.bit.INT = 1;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}


__interrupt void epwm3_isr(void)
{
    EPwm3Regs.CMPA.bit.CMPA = EPwm3Regs.TBPRD-SineTable[IntCount]/2;    // Set compare A value
            EPwm3Regs.CMPB.bit.CMPB = EPwm3Regs.TBPRD-SineTable[IntCount]/2;    // Set Compare B value
            if( IntCount < 100)
              {
               IntCount++;
           }
           else
            IntCount = 0;
    // Clear INT flag for this timer
    //
    EPwm3Regs.ETCLR.bit.INT = 1;

    //
    // Acknowledge this interrupt to receive more interrupts from group 3
    //
    PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}

//
// InitEPwm1Example - Initialize EPWM1 configuration
//
void InitEPwm1Example()
{
    //unsigned long IntCount = 0;
    //
    // Setup TBCLK
    //

    EPwm1Regs.TBPRD = EPWM1_TIMER_TBPRD;       // Set timer period 801 TBCLKs
    EPwm1Regs.TBPHS.bit.TBPHS = 0x0000;        // Phase is 0
    EPwm1Regs.TBCTR = 0x0000;                  // Clear counter

    //
    // Set Compare values
    //
    EPwm1Regs.CMPA.bit.CMPA = EPwm1Regs.TBPRD/2; //SineTable[IntCount];    // Set compare A value
    EPwm1Regs.CMPB.bit.CMPB = EPwm1Regs.TBPRD/2; //SineTable[IntCount];    // Set Compare B value
    //EPwm1Regs.CMPA.bit.CMPA = 0x200;
      //      EPwm1Regs.CMPB.bit.CMPB = 0x300;

    //
    // Setup counter mode
    //
    EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up and down
    EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;        // Disable phase loading
    EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;       // Clock ratio to SYSCLKOUT
    EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;

    //
    // Set actions
    //
    EPwm1Regs.AQCTLA.bit.CAU = AQ_SET;            // Set PWM1A on event A, up
                                                  // count
    EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR;          // Clear PWM1A on event A,
                                                  // down count

    EPwm1Regs.AQCTLB.bit.CBU = AQ_SET;            // Set PWM1B on event B, up
                                                  // count
    EPwm1Regs.AQCTLB.bit.CBD = AQ_CLEAR;          // Clear PWM1B on event B,
                                                  // down count

    //
    // Interrupt where we will change the Compare Values
    //
    EPwm1Regs.ETSEL.bit.INTSEL = 4;     // Select INT on TBCTR = CMPA up-count
    EPwm1Regs.ETSEL.bit.INTEN = 1;                // Enable INT
    EPwm1Regs.ETPS.bit.INTPRD = 1;           // Generate INT on 3rd event
}

void InitEPwm2Example()
{
    //unsigned long IntCount = 0;
    //
    // Setup TBCLK
    //
    EPwm2Regs.TBPRD = EPWM2_TIMER_TBPRD;       // Set timer period 801 TBCLKs
    EPwm2Regs.TBPHS.bit.TBPHS = 0x0000;        // Phase is 0
    EPwm2Regs.TBCTR = 0x0000;                  // Clear counter

    //
    // Set Compare values
    //
    EPwm2Regs.CMPA.bit.CMPA = EPwm2Regs.TBPRD/2; //SineTable[IntCount];    // Set compare A value
    EPwm2Regs.CMPB.bit.CMPB = EPwm2Regs.TBPRD/2; //SineTable[IntCount];    // Set Compare B value
    //
     // Setup counter mode
     //
     EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up and down
     EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE;        // Disable phase loading
     EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;       // Clock ratio to SYSCLKOUT
     EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;

     //
     // Set actions
     //
     EPwm2Regs.AQCTLA.bit.CAU = AQ_SET;            // Set PWM1A on event A, up
                                                   // count
     EPwm2Regs.AQCTLA.bit.CAD = AQ_CLEAR;          // Clear PWM1A on event A,
                                                   // down count

     EPwm2Regs.AQCTLB.bit.CBU = AQ_SET;            // Set PWM1B on event B, up
                                                   // count
     EPwm2Regs.AQCTLB.bit.CBD = AQ_CLEAR;          // Clear PWM1B on event B,
                                                   // down count

     //
     // Interrupt where we will change the Compare Values
     //
     EPwm2Regs.ETSEL.bit.INTSEL = 4;     // Select INT on TBCTR = CMPA up-count
     EPwm2Regs.ETSEL.bit.INTEN = 1;                // Enable INT
     EPwm2Regs.ETPS.bit.INTPRD = 1;           // Generate INT on 3rd event
 }


void InitEPwm3Example()
{
    //unsigned long IntCount = 0;
    //
    // Setup TBCLK
    //
    EPwm3Regs.TBPRD = EPWM3_TIMER_TBPRD;       // Set timer period 801 TBCLKs
    EPwm3Regs.TBPHS.bit.TBPHS = 0x0000;        // Phase is 0
    EPwm3Regs.TBCTR = 0x0000;                  // Clear counter

    //
    // Set Compare values
    //
    EPwm3Regs.CMPA.bit.CMPA = EPwm3Regs.TBPRD/2; //SineTable[IntCount];    // Set compare A value
    EPwm3Regs.CMPB.bit.CMPB = EPwm3Regs.TBPRD/2; //SineTable[IntCount];    // Set Compare B value

    //
    // Setup counter mode
    //
    EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up and down
    EPwm3Regs.TBCTL.bit.PHSEN = TB_DISABLE;        // Disable phase loading
    EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;       // Clock ratio to SYSCLKOUT
    EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;
    //
    // Set actions
    //
    EPwm3Regs.AQCTLA.bit.CAU = AQ_SET;            // Set PWM1A on event A, up
                                                  // count
    EPwm3Regs.AQCTLA.bit.CAD = AQ_CLEAR;          // Clear PWM1A on event A,
                                                  // down count

    EPwm3Regs.AQCTLB.bit.CBU = AQ_SET;            // Set PWM1B on event B, up
                                                  // count
    EPwm3Regs.AQCTLB.bit.CBD = AQ_CLEAR;          // Clear PWM1B on event B,
                                                  // down count
    //
    // Interrupt where we will change the Compare Values
    //
    EPwm3Regs.ETSEL.bit.INTSEL = 4;     // Select INT on TBCTR = CMPA up-count
    EPwm3Regs.ETSEL.bit.INTEN = 1;                // Enable INT
    EPwm3Regs.ETPS.bit.INTPRD = 1;           // Generate INT on 3rd event
}



void Gpio_setup (void)
{
    EALLOW;
    GpioCtrlRegs.GPBMUX2.bit.GPIO63 = 0;//GPIO
    GpioCtrlRegs.GPBDIR.bit.GPIO63 = 1; //output
    EDIS;
}

Richard,

             I put a breakpoint on line 99. As I am running the code there is no increment in register values at this breakpoint is not incrementing or showing any value.

Thank you

Bighnaraj Panda 

Bighnaraj,

I wasn't asking about the registers. All I wanted to know was whether you are reaching the break point every time you run the program.  I'm going to assume you are reaching the BP.  If that is wrong please let me know; otherwise, here is what you need to look at.

Your initial problem was CMPA/B being loaded with values larger than TBPRD. This meant the PWM interrupts, which are initially configured on a CMPA up-count event, never happened. The reason CMPx registers were being wrongly loaded was the IntCount variable was not initialized. I explained you need to initialilze the global variable and I believe you have done that now.

The first entry in your look-up table is zero. Normally this would not cause an issue, but your code is toggling the interrupt trigger between CMPA up-count and CMPB down-count. When the threshold is zero this causes an interrupt to be generated which is not acknowledged at the PIE level, and the interrupt stops. If you comment out lines 109 and 120, you will probably find the interrupts work normally. I have not analyzed the reason why you are losing an interrupt, but I suggest trying this first to be sure you get interrupts reliably before moving on.

I do not know the integrity of the look-up table. I understand you found it from another forum thread. I observe you are loading TBPRD with 2500, and the upper 16 bits of most entries in the table are larger than that, meaning you won't get interrupts when you load those values into the CMPx registers. You need to think about what's in the table relative to the TBPRD register.

If it's of interest, you may like to look at the sine table in lab 4 of the 1-day workshop of the device you are using. I have attached that file, and you can find other workshop materials here:
training.ti.com/c2000-workshops

I hope this helps.

Regards,

Richard

Attached file.

/* sinetab.c */

// table section declaration
// #pragma DATA_SECTION(QuadratureTable,"QuadratureTableSection")

// quadrature look-up table: contains 5 quadrants of sinusoid data points
int QuadratureTable[40] = {
		0x0000,			// [0]  0
		0x18F8,	        // [1]  11.25
		0x30FB,	        // [2]  22.50
		0x471C,	        // [3]  33.75
		0x5A81,	        // [4]  45.00
		0x6A6C,	        // [5]  56.25
		0x7640,	        // [6]  67.50
		0x7D89,	        // [7]  78.75
		0x7FFF,	        // [8]  90.00
		0x7D89,	        // [9]  78.75
		0x7640,	        // [10] 67.50
		0x6A6C,	        // [11] 56.25
		0x5A81,	        // [12] 45.00
		0x471C,	        // [13] 33.75
		0x30FB,	        // [14] 22.50
		0x18F8,	        // [15] 11.25
		0x0000,	        // [16] 0
		0xE708,	        // [17] -11.25
		0xCF05,	        // [18] -22.50
		0xB8E4,	        // [19] -33.75
		0xA57F,        	// [20] -45.00
		0x9594,	        // [21] -56.25
		0x89C0,	        // [22] -67.50
		0x8277,	        // [23] -78.75
		0x8000,        	// [24] -90.00
		0x8277,	        // [25] -78.75
		0x89C0,	        // [26] -67.50
		0x9594,	        // [27] -56.25
		0xA57F,	        // [28] -45.00
		0xB8E4,         // [29] -33.75
		0xCF05,	        // [30] -22.50
		0xE708,	        // [31] -11.25
		0x0000,			// [32] 0
		0x18F8,	        // [33] 11.25
		0x30FB,	        // [34] 22.50
		0x471C,	        // [35] 33.75
		0x5A81,	        // [36] 45.00
		0x6A6C,	        // [37] 56.25
		0x7640,	        // [38] 67.50
		0x7D89 	        // [39] 78.75
		};

/* end of file */