Other Parts Discussed in Thread: SYSBIOS
Tool/software: Code Composer Studio
Hi,
A few days ago, I found the timer interruption unstable during a test. First, I suspect the HWI DISPATCHER caused it.
So, I turn to TI for help. With the help of Sahin, I achieved an interrupt without DISPATCHER. The method can be found here.
https://e2e.ti.com/support/legacy_forums/embedded/tirtos/f/355/t/372449
Unfortunately, the problem has not been solved.The timer interrupt function is not stable.For the latest test I used external interrupts.
Trigger signal is generated by FPGA. I have found that each unstable clock cycle approaches the correct value multiple.
So I wonder if the interrupt DISABLE of the SYSBIOS caused the instability.
Is there any one who can give me some guidance?
Interrupt cycle 10us
Regards,
Dor