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CCS/TMS320C6748: Does I2C_Slave_lcdkOMAPL138_c674xTestProject project support I2C slave mode?

Shin MinCheol
Prodigy 220 points

Part Number: TMS320C6748

Tool/software: Code Composer Studio

Hi,

Does I2C_Slave_lcdkOMAPL138_c674xTestProject project support I2C slave mode?

As in the example, the SCL, SDA, and GND hardware pins are connected, and the current counterpart, the master, sends the address.

However, since the NACK signal does not come, data is not transmitted later.

In the example code, proceed to I2C master slave test master in non-dma interrupt mode, and of course, the slave addresses matched each other.

Line 436, transferOK = I2C_transfer (i2c, & transaction);

The transfer function waits indefinitely. (The data is continuously transferred from the partner board.)

In the example project, except for the slave address, almost nothing has changed. What is the problem?

If you look at the 5.6 I2C Driver in the TI-RTOS 2.20 User's Guide guide, it says that it does not support I2C slave mode.

Does TMS320C6748 TI-RTOS support I2C slave mode?

  • 0
    TI__Mastermind 27355 points

    Hello and sorry for the delayed response,

    Yes, I2C slave mode is supported in Processor SDK RTOS, which is built upon TI-RTOS. Documentation on the I2C driver in Processor SDK can be found here: http://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/index_device_drv.html#i2c

    Some questions:

    Are you using a TI EVM or custom hardware?

    Have you already referred to the following I2C page?

    https://processors.wiki.ti.com/index.php/I2C_Tips#External_Slave_Device_Hanging_the_Bus_by_Holding_SDA_Low

    What is the master device in this case? 

    If you could provide a I2C register dump before and after the hang that may help as well.

    Regards,
    Sahin

  • 0 in reply to Sahin Okur
    Prodigy 220 points

    * Are you using a TI EVM or custom hardware?

       EFM32 EVM I2C Mater-TMS320C6748 EVM I2C Slave mode.

    Since the NACK signal does not come, communication ends at the device address.

    Conversely, TMS320C6748 EVM I2C Master-EFM32 EVM I2C Slave communication is successful.

    * If you could provide a I2C register dump before and after the hang that may help as well.

       What can I2C register dump show specifically? CCS register view?

    Line 436, transferOK = I2C_transfer (i2c, & transaction);

    In any case, why is it usually waiting indefinitely in the code above?

    Since the NACK signal is not received, the clock cannot be continuously sent from the master's point of view.

    It works with example code, but I don't know what I missed.

  • 0 in reply to Shin MinCheol
    TI__Mastermind 27355 points

    Hello,

    Unfortunately I do not have access to a second board to test this at the moment so the best I can do is provide suggestions, I apologize for this.

    The reason for the register dump is that I'm curious to see if there are any interrupt flags set (ICSTR register) that may give us some clues. The CCS register view will show this. 

    You mentioned the NACK signal does not come, do you have scope shots you can share? 

    To initiate a transfer the master device will generate a start condition by transitioning SDA high to low while SCL is high. This is followed by a byte containing the slave device address and a read/write bit. When the slave device has received the correct address and the read/write bit, it will drive SDA low as an ack that it received the information correctly. Do you see the C6748 drive SDA low after the first byte?

    What are you setting the device address to on the master side? Please share a code snippet if you can. Remember it is 7-bits so it should be left shifted by one bit. For example, if the slave address is 0x20, you should put 0x40 for reads and 0x41 for writes on the master side. 

    Also, ensure you are running the slave code on the C6748 before running the master code.

    Regards,
    Sahin