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Compiler/TMS320F28388D: CLA task does not run when code size reaches certain size

Huey Duong
Intellectual 340 points
Part Number: TMS320F28388D
Other Parts Discussed in Thread: TMDSCNCD28388D, C2000WARE

Tool/software: TI C/C++ Compiler

Eval board: F28388D controlCARD (TMDSCNCD28388D) 

Running control algorithm CLA1 and using GPIO28 to confirm CLA task 1 is executing periodically.

When CLA code size is of a certain size, CLA-task1 runs.  But once I increase the code size by adding a single MNOP, the CLA-task1 no longer runs as GPIO28 does not toggle.

(See below, commented out MNOP)

CLA should not have any restrictions on task code size, other than available memory.

In the map files, once ClaTask1 goes from 0x54c to 0x54e.  Or Cla1Prog from 0x584 to 0x586  the CLA task does not run.

Here are some supporting information:

Compiler and linker options:

-v28 -ml -mt --cla_support=cla2 --float_support=fpu64 --idiv_support=idiv0 --tmu_support=tmu0 --vcu_support=vcu2 -O2 --opt_for_speed=2 --fp_mode=relaxed --fp_reassoc=on --include_path="gen3_dsp/gen3_pjt" --include_path="gen3_dsp/gen3_pjt/inc/hal" --include_path="gen3_dsp/gen3_pjt/inc/cli" --include_path="gen3_dsp/gen3_pjt/inc/core" --include_path="gen3_dsp/gen3_pjt/inc/control" --include_path="C:/ti/ccs930/ccs/tools/compiler/ti-cgt-c2000_18.12.5.LTS/include" --include_path="gen3_dsp/vendor/ti/C2000Ware/device_support/f2838x/headers/include" --include_path="gen3_dsp/vendor/ti/C2000Ware/device_support/f2838x/common/include" --include_path="gen3_dsp/vendor/ti/C2000Ware/libraries/math/CLAmath/c28/include" --include_path="gen3_dsp/vendor/ti/C2000Ware/driverlib/f2838x/driverlib" --include_path="gen3_dsp/vendor/ti/C2000Ware/driverlib/f2838x/driverlib/inc" --advice:performance=all --define=_FLASH --define=DEBUG --define=CPU1 -g --c11 --printf_support=minimal --diag_suppress=10063 --diag_warning=225 --diag_wrap=off --display_error_number --gen_func_subsections=on --abi=eabi --cla_signed_compare_workaround=on -k --asm_listing

-v28 -ml -mt --cla_support=cla2 --float_support=fpu64 --idiv_support=idiv0 --tmu_support=tmu0 --vcu_support=vcu2 -O2 --opt_for_speed=2 --fp_mode=relaxed --fp_reassoc=on --advice:performance=all --define=_FLASH --define=DEBUG --define=CPU1 -g --c11 --printf_support=minimal --diag_suppress=10063 --diag_warning=225 --diag_wrap=off --display_error_number --gen_func_subsections=on --abi=eabi --cla_signed_compare_workaround=on -k --asm_listing -z -m"gen3_pjt.map" --heap_size=0x800 --stack_size=0x640 --warn_sections -i"C:/ti/ccs930/ccs/tools/compiler/ti-cgt-c2000_18.12.5.LTS/lib" -i"C:/ti/ccs930/ccs/tools/compiler/ti-cgt-c2000_18.12.5.LTS/include" --reread_libs --diag_wrap=off --display_error_number --xml_link_info="gen3_pjt_linkInfo.xml" --entry_point=code_start --rom_model

Linker file:

MEMORY

{
/* BEGIN is used for the "boot to Flash" bootloader mode */
BEGIN : origin = 0x080000, length = 0x000002
BOOT_RSVD : origin = 0x000002, length = 0x0001AE /* Part of M0, BOOT rom will use this for stack */
RAMM0M1 : origin = 0x0001B0, length = 0x000648
// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

CLA1_MSGRAMLOW : origin = 0x001480, length = 0x000080
CLA1_MSGRAMHIGH : origin = 0x001500, length = 0x000080

RAMLS0LS1 : origin = 0x008000, length = 0x001000
RAMLS2LS3LS4LS5 : origin = 0x009000, length = 0x002000
RAMLS6 : origin = 0x00B000, length = 0x000800
RAMLS7 : origin = 0x00B800, length = 0x000800

RAMD0 : origin = 0x00C000, length = 0x000800
RAMD1 : origin = 0x00C800, length = 0x000800

RAMGS0 : origin = 0x00D000, length = 0x001000
RAMGS1 : origin = 0x00E000, length = 0x001000
RAMGS2 : origin = 0x00F000, length = 0x001000
RAMGS3 : origin = 0x010000, length = 0x001000
RAMGS4 : origin = 0x011000, length = 0x001000
RAMGS5 : origin = 0x012000, length = 0x001000
RAMGS6 : origin = 0x013000, length = 0x001000
RAMGS7 : origin = 0x014000, length = 0x001000
RAMGS8 : origin = 0x015000, length = 0x001000
RAMGS9 : origin = 0x016000, length = 0x001000
RAMGS10 : origin = 0x017000, length = 0x001000
RAMGS11 : origin = 0x018000, length = 0x001000
RAMGS12 : origin = 0x019000, length = 0x001000
RAMGS13 : origin = 0x01A000, length = 0x001000
RAMGS14 : origin = 0x01B000, length = 0x001000
RAMGS15 : origin = 0x01C000, length = 0x000FF8
// RAMGS15_RSVD : origin = 0x01CFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

CPU1TOCPU2RAM : origin = 0x03A000, length = 0x000800
CPU2TOCPU1RAM : origin = 0x03B000, length = 0x000800
CPUTOCMRAM : origin = 0x039000, length = 0x000800
CMTOCPURAM : origin = 0x038000, length = 0x000800

CANA_MSG_RAM : origin = 0x049000, length = 0x000800
CANB_MSG_RAM : origin = 0x04B000, length = 0x000800

/* Flash sectors */
FLASH0 : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
FLASH1 : origin = 0x082000, length = 0x002000 /* on-chip Flash */
FLASH2 : origin = 0x084000, length = 0x002000 /* on-chip Flash */
FLASH3 : origin = 0x086000, length = 0x002000 /* on-chip Flash */
FLASH4 : origin = 0x088000, length = 0x008000 /* on-chip Flash */
FLASH5 : origin = 0x090000, length = 0x008000 /* on-chip Flash */
FLASH6 : origin = 0x098000, length = 0x008000 /* on-chip Flash */
FLASH7 : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
FLASH8 : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
FLASH9 : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
FLASH10 : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
FLASH11 : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
FLASH12 : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
FLASH13 : origin = 0x0BE000, length = 0x001FF0 /* on-chip Flash */
// FLASH13_RSVD : origin = 0x0BFFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

RESET : origin = 0x3FFFC0, length = 0x000002
}

SECTIONS
{
codestart : > BEGIN, ALIGN(4)
.text : >> FLASH1 | FLASH2 | FLASH3 | FLASH4, ALIGN(4)
.cinit : > FLASH4, ALIGN(4)
.switch : > FLASH1, ALIGN(4)
.reset : > RESET, TYPE = DSECT /* not used, */
.stack : > RAMM0M1

#if defined(__TI_EABI__)
.init_array : > FLASH1, ALIGN(4)
.bss : >> RAMGS0 | RAMGS1, ALIGN(4)
.bss:output : > RAMGS0
.bss:cio : > RAMGS0
.data : > RAMGS1
.sysmem : > RAMGS1
/* Initalized sections go in Flash */
.const : > FLASH5, ALIGN(4)
#else
.pinit : > FLASH1, ALIGN(4)
.ebss : > RAMGS0
.esysmem : > RAMGS1
.cio : > RAMGS1
/* Initalized sections go in Flash */
.econst : >> FLASH4 | FLASH5, ALIGN(4)
#endif

#if defined(__TI_EABI__)
.TI.ramfunc : {} LOAD = FLASH3,
RUN = RAMD0,
LOAD_START(RamfuncsLoadStart),
LOAD_SIZE(RamfuncsLoadSize),
LOAD_END(RamfuncsLoadEnd),
RUN_START(RamfuncsRunStart),
RUN_SIZE(RamfuncsRunSize),
RUN_END(RamfuncsRunEnd),
ALIGN(4)
#else
.TI.ramfunc : {} LOAD = FLASH3,
RUN = RAMD0,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
ALIGN(4)
#endif

MSGRAM_CPU1_TO_CPU2 : > CPU1TOCPU2RAM, type=NOINIT

MSGRAM_CPU2_TO_CPU1 : > CPU2TOCPU1RAM, type=NOINIT
MSGRAM_CPU_TO_CM : > CPUTOCMRAM, type=NOINIT
MSGRAM_CM_TO_CPU : > CMTOCPURAM, type=NOINIT


/* CLA specific sections */

Cla1ToCpuMsgRAM : > CLA1_MSGRAMLOW, type=NOINIT

CpuToCla1MsgRAM : > CLA1_MSGRAMHIGH, type=NOINIT

.scratchpad : > RAMLS0LS1

.bss_cla : > RAMLS0LS1
cpu1_cla1_shared : > RAMLS0LS1

#if defined(__TI_EABI__)
.const_cla : LOAD = FLASH2,
RUN = RAMLS2LS3LS4LS5,
RUN_START(Cla1ConstRunStart),
LOAD_START(Cla1ConstLoadStart),
LOAD_SIZE(Cla1ConstLoadSize)
#else
.const_cla : LOAD = FLASH2,
RUN = RAMLS2LS3LS4LS5,
RUN_START(_Cla1ConstRunStart),
LOAD_START(_Cla1ConstLoadStart),
LOAD_SIZE(_Cla1ConstLoadSize)
#endif

#if defined(__TI_EABI__)
Cla1Prog : LOAD = FLASH7,
RUN = RAMLS2LS3LS4LS5,
LOAD_START(Cla1funcsLoadStart),
LOAD_END(Cla1funcsLoadEnd),
RUN_START(Cla1funcsRunStart),
LOAD_SIZE(Cla1funcsLoadSize),
ALIGN(4)
#else
Cla1Prog : LOAD = FLASH7,
RUN = RAMLS2LS3LS4LS5,
LOAD_START(_Cla1funcsLoadStart),
LOAD_END(_Cla1funcsLoadEnd),
RUN_START(_Cla1funcsRunStart),
LOAD_SIZE(_Cla1funcsLoadSize),
ALIGN(4)
#endif

}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

CLA init code

void claHal_init(void)
{
extern uint32_t Cla1funcsRunStart, Cla1funcsLoadStart, Cla1funcsLoadSize;
extern uint32_t Cla1ConstRunStart, Cla1ConstLoadStart, Cla1ConstLoadSize;

EALLOW;

#ifdef _FLASH
memcpy((uint32_t *)&Cla1funcsRunStart, (uint32_t *)&Cla1funcsLoadStart,
(uint32_t)&Cla1funcsLoadSize);

memcpy((uint32_t *)&Cla1ConstRunStart, (uint32_t *)&Cla1ConstLoadStart,
(uint32_t)&Cla1ConstLoadSize );

#endif //_FLASH

MemCfgRegs.MSGxINIT.bit.INIT_CLA1TOCPU = 1;
while(MemCfgRegs.MSGxINITDONE.bit.INITDONE_CLA1TOCPU != 1){};

MemCfgRegs.MSGxINIT.bit.INIT_CPUTOCLA1 = 1;
while(MemCfgRegs.MSGxINITDONE.bit.INITDONE_CPUTOCLA1 != 1){};

MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS0 = 0U;
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS1 = 0U;
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS2 = 1U;
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS3 = 1U;
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS4 = 1U;
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS5 = 1U;

MemCfgRegs.LSxMSEL.bit.MSEL_LS0 = 1U;
MemCfgRegs.LSxMSEL.bit.MSEL_LS1 = 1U;
MemCfgRegs.LSxMSEL.bit.MSEL_LS2 = 1U;
MemCfgRegs.LSxMSEL.bit.MSEL_LS3 = 1U;
MemCfgRegs.LSxMSEL.bit.MSEL_LS4 = 1U;
MemCfgRegs.LSxMSEL.bit.MSEL_LS5 = 1U;

#pragma diag_suppress 770

Cla1Regs.MVECT1 = (uint16_t)(&Cla1Task1);
Cla1Regs.MVECT2 = (uint16_t)(&Cla1Task2);
Cla1Regs.MVECT3 = (uint16_t)(&Cla1Task3);
Cla1Regs.MVECT4 = (uint16_t)(&Cla1Task4);
Cla1Regs.MVECT5 = (uint16_t)(&Cla1Task5);
Cla1Regs.MVECT6 = (uint16_t)(&Cla1Task6);
Cla1Regs.MVECT7 = (uint16_t)(&Cla1Task7);
Cla1Regs.MVECT8 = (uint16_t)(&Cla1Task8);
#pragma diag_default 770

DmaClaSrcSelRegs.CLA1TASKSRCSEL1.bit.TASK1 = CLA_TRIGGER_ADCD1;

Cla1Regs.MIER.bit.INT1 = 1U;

Cla1Regs.MCTL.bit.IACKE = 1;
Cla1Regs.MIER.all = 0x00FF;

PieVectTable.CLA1_1_INT = &claHal_doneIsr1;
PieVectTable.CLA1_2_INT = &claHal_doneIsr2;
PieVectTable.CLA1_3_INT = &claHal_doneIsr3;
PieVectTable.CLA1_4_INT = &claHal_doneIsr4;
PieVectTable.CLA1_5_INT = &claHal_doneIsr5;
PieVectTable.CLA1_6_INT = &claHal_doneIsr6;
PieVectTable.CLA1_7_INT = &claHal_doneIsr7;
PieVectTable.CLA1_8_INT = &claHal_doneIsr8;

PieCtrlRegs.PIEIER11.all = 0xFFFF;
IER |= (M_INT11 );


GPIO_setMasterCore(28, GPIO_CORE_CPU1_CLA1);

EDIS;
}

  • 0
    TI__Guru* 92140 points

    Hello,

    Some things to check:

    1. Does the task run at least once? 
    2. What do the CLA flags indicate when the task doesn't run?  Is the flag set? Is the task overflow flag set?  It may be that interrupts are coming in faster than it takes the interrupt to complete.
    3. If the task is being triggered by a peripheral, you can try triggering it with software and see if it runs.  That will point to whether the problem is in triggering the task or the task itself. 

    Regards

    Lori

  • 0 in reply to Lori Heustess
    Intellectual 340 points

    Thank you for the fast response. 

    Great suggestions.

    1. No the task does not run even once.

    2. When running ADCD4 EOC is configured to trigger CLA task1:

    CLA Regs: MIER=0xff, MIFR=0, MIOVF=0

    CPU1 Regs: IER=0x1401, IFR= 0, PIEIER1=0x5d, PIEIFR1=0x20, ADC4Regs: ADCINTSEL1N2=0x24, ADCINTFLG=0x1, ADCINTOVF=0x01

    Looks like I have an ADCINT1 overflow.

    3. I added a call to force the task to run in mainloop and it worked.  The CLA task starts to run periodically from the ADC EOC interrupt.

    Looks like have some timing issue with setting up interrupts / clearing flags.

    The code size issues must be a red herring that changed my timing when copying Cla1Prog from flash to memory.

    Thanks for the great suggestions, I will look into interrupts more and get back to this thread on my results.

  • 0 in reply to Huey Duong
    Intellectual 340 points

    I moved the cla_init() code to before the adc_init() code and everything worked fine.

        device_init();
    claHal_init();   <<< New CLA init
    sciHal_init();
    gpioHal_init();
    dio_init();
    pwmHal_init();
    adcHal_init();   <<< ADC INIT
    dacHal_init();
    ctrl_init();
    timerHal_init();
    // claHal_init(); <<< Original CLA init with ADC int OVF

    EINT;
    ERTM;

    It works fine now even with Cla1Prog size of 0x101a.

    Thanks!!