CCS/PROCESSOR-SDK-DRA8X-TDA4X: Ethernet Loop Back Test on TDA4x hangs on the Bios_start()

Vijender Saini

Part Number: PROCESSOR-SDK-DRA8X-TDA4X

Tool/software: Code Composer Studio

Dear sir,

I am working on ehternet frame work for CPSW2G on TDA4x Board. I run the the Loop back test on the board through the CCS. So i load the image "cpsw_loopback_testapp_mcu1_0_release.xer5f" on the board.

But program hangs on the Bios_start() function. Some important points of experiment given below

1. I do not have GESI board.

2. Sw8 and Sw9 is set according to no boot mode

3. No messages display on the UART(J44).

4. Using PSDK 6.1

Give me the Suggenstions how to run the Loopback test on the TDA4x.

Thank you

Vijender

over 6 years ago

0 Prasad Jondhale over 6 years ago

TI__Mastermind 27743 points

Hello Vijender,

Vijender Saini said:

3. No messages display on the UART(J44).

Seems you are connecting wrong UART. You need to use MCU UART and not MAIN UART when running apps on mcu1_0 core.

If this doesn't work, can you please provide more information about your test set up?

- Which core you are test application?

- Are you able to see sysfw load messages on CCS console?

0 Vijender Saini over 6 years ago in reply to Prasad Jondhale

Intellectual 860 points

Hello Prasad

Thank you for your quick Reply.

- Which core you are test application? ----> MCU_Cortex_R5_0 (mcu1_0)

- Are you able to see sysfw load messages on CCS console? ----> Yes, you can see the messages in attach file(Console_messages.txt)

I changed the Uart from MAIN UART to MCU UART. Now got some information in Hex and all the messages have not lined up.

MCU UART messages shown below.

0x61C00123 0x420201 0x820003 0x61800201 0x61C00124 0x420201 0x820003 0x61800201 0x61C 00125 0x420201 0x820003 0x61800201 0x61C00126 0x420201 0x820003 0x61800201 0x61C00127 0x420201 0x820 003 0x61 800201 0x61C00129 FWL Bit 0x30 Exception addr 0x45B04000 FWL Exception 0x1188000 0x10000 0x 2B0AC438 0x0 0xFF91B60 0x4
FWL Bit 0x30 Exception addr 0x45B04000 FWL Exception 0x1188000 0x10000
0x2B0AC438 0x0 0xFF91B60 0x4
FWL Bit 0x30 Exception addr 0x45B04000 FWL Exception 0x11880 00 0x10000 0x2B0AC438 0x0 0xFF91B60 0x4

FWL Bit 0x30 Exception addr 0x45B04000 FWL Exceptio n 0x11 88000 0x10000 0x2B0AC438 0x0 0xFF91B60 0x4

Fullscreen Console_messages.txt Download

DMSC_Cortex_M3_0: GEL Output: Configuring ATCM for the R5Fs
DMSC_Cortex_M3_0: GEL Output: ATCM Configured.
DMSC_Cortex_M3_0: GEL Output: This GEL is currently only supported for use from the Cortex-M3 inside the DMSC.
DMSC_Cortex_M3_0: GEL Output: Do not run this GEL from any other CPU on the SoC.
DMSC_Cortex_M3_0: GEL Output: This script sets the first address translation region to [0x8000_0000, 0x0000_0000].
DMSC_Cortex_M3_0: GEL Output: It also sets the second address translation region to [0x6000_0000, 0x4000_0000].
DMSC_Cortex_M3_0: GEL Output: This is consistent with the SoC DV assumptions.
DMSC_Cortex_M3_0: GEL Output: C66xx_0 configured for Wait In Reset Mode
DMSC_Cortex_M3_0: GEL Output: C66xx_1 configured for Wait In Reset Mode
DMSC_Cortex_M3_0: GEL Output: C71x_0 configured for Wait In Reset Mode
DMSC_Cortex_M3_0: GEL Output: R5F Halt bits set.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_WKUPMCU2MAIN
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Checking LPSC_WKUPMCU2MAIN
DMSC_Cortex_M3_0: GEL Output: Power Domain: On
DMSC_Cortex_M3_0: GEL Output: Module State: Enable
DMSC_Cortex_M3_0: GEL Output: Programming all PLLs.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 0 (Main PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 0 (Main PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 1 (Peripheral 0 PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 1 (Peripheral 0 PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 2 (Peripheral 1 PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 2 (Peripheral 1 PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 3 (CPSW9G PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 3 (CPSW9G PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 4 (Audio 0 PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 4 (Audio 0 PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 5 (Video PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 5 (Video PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 6 (GPU PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 6 (GPU PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 7 (C7x PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 7 (C7x PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 8 (ARM0 PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 8 (ARM0 PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 12 (DDR PLL)
DMSC_Cortex_M3_0: GEL Output: DDR PLL Calibration Control MMR value: 0x80170000
DMSC_Cortex_M3_0: GEL Output: DDR PLL Calibration Control MMR value: 0x800001F4
DMSC_Cortex_M3_0: GEL Output: Main PLL 12 (DDR PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 13 (C66x PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 13 (C66x PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 14 (Main Domain Pulsar) PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 14 (Main Domain Pulsar PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 15 (Audio 1 PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 15 (Audio 1 PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 16 (DSS0 PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 16 (DSS0 PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 17 (DSS1 PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 17 (DSS1 PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 18 (DSS2 PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 17 (DSS2 PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 19 (DSS3 PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 19 (DSS3 PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 23 (DSS7 PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 23 (DSS7 PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 25 (Vision PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 25 (Vision PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming MCU PLL 0 (MCU PLL)
DMSC_Cortex_M3_0: GEL Output: MCU PLL 0 (MCU PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming MCU PLL 1 (MCU Peripheral PLL)
DMSC_Cortex_M3_0: GEL Output: MCU PLL 1 (MCU PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming MCU PLL 2 (MCU CPSW PLL)
DMSC_Cortex_M3_0: GEL Output: MCU PLL 2 (MCU PLL) Set.
DMSC_Cortex_M3_0: GEL Output: All PLLs programmed.
DMSC_Cortex_M3_0: GEL Output: Powering up all PSC power domains in progress...
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_WKUP_ALWAYSON
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DMSC
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DEBUG2DMSC
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_WKUP_GPIO
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_WKUPMCU2MAIN
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_TEST
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_DEBUG
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_MCAN_0
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_MCAN_1
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_OSPI_0
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_OSPI_1
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_HYPERBUS
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_I3C_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_I3C_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_ADC_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_ADC_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_R5_0
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_R5_1
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_PULSAR_PBIST_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_ALWAYSON
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_TEST
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_PBIST
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PER_AUDIO
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PER_ATL
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PER_MLB
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PER_MOTOR
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PER_MISCIO
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PER_GPMC
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PER_VPFE
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PER_VPE
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_DEBUG
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMIF_CFG_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMIF_DATA_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMIF_CFG_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMIF_DATA_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DMTIMER_0
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DMTIMER_1
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DMTIMER_2
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DMTIMER_3
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MMC4B_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MMC4B_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MMC8B_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_UFS_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_UFS_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SAUL
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PER_I3C
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_2
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_3
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_4
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_5
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_6
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_7
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_8
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_9
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_10
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_11
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_12
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_13
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SERDES_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SERDES_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SERDES_2
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SERDES_3
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SERDES_4
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SERDES_5
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_USB_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_USB_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_USB_2
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PCIE_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PCIE_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PCIE_2
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PCIE_3
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ICSSG_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ICSSG_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_9GSS
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DSS_PBIST
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DSS
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_TX_DPHY_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DSI
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EDP_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EDP_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_CSITX_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_CSIRX_PHY_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_CSIRX_PHY_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_CSIRX_PHY_2
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_CSIRX_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_CSIRX_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_CSIRX_2
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_C71X_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_C71X_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_C71X_0_PBIST
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_C71X_1_PBIST
DMSC_Cortex_M3_0: GEL Output: ERROR: module state NOT changed!
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A72_CLUSTER_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A72_CLUSTER_0_PBIST
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A72_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A72_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A72_CLUSTER_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A72_CLUSTER_1_PBIST
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A72_2
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A72_3
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_GPUCOM
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_GPUPBIST
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_GPUCORE
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_C66X_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_C66X_PBIST_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_C66X_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_C66X_PBIST_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_0_R5_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_0_R5_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_0_PBIST
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_1_R5_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_1_R5_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_1_PBIST
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DECODE_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DECODE_PBIST
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ENCODE_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ENCODE_PBIST
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DMPAC
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SDE
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DMPAC_PBIST
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_VPAC
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_VPAC_PBIST
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up all PSC power domains done!
DMSC_Cortex_M3_0: GEL Output: Configuring drive strength.
DMSC_Cortex_M3_0: GEL Output: First, unlock the MMRs.
DMSC_Cortex_M3_0: GEL Output: Unlocked MMRs.
DMSC_Cortex_M3_0: GEL Output: Configuring horizontal drive strength.
DMSC_Cortex_M3_0: GEL Output: Horizontal drive strength configured.
DMSC_Cortex_M3_0: GEL Output: Configuring vertical drive strength.
DMSC_Cortex_M3_0: GEL Output: Vertical drive strength configured.
DMSC_Cortex_M3_0: GEL Output: LVCMOS drive strength configured to 0xD
DMSC_Cortex_M3_0: GEL Output: --->>> LPDDR4 Initialization is in progress ... <<<---
DMSC_Cortex_M3_0: GEL Output: Setting DDR PLL to 20MHz/19.2MHz on silicon (bypass)
DMSC_Cortex_M3_0: GEL Output: Set PLL to external bypass (20MHz/19.2MHz on SVB/EVM).
DMSC_Cortex_M3_0: GEL Output: --->>> DDR controller programming in progress.. <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> DDR controller programming completed... <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> DDR PI programming in progress.. <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> DDR PI programming completed... <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> DDR PHY Data Slice 0 programming in progress.. <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> DDR PHY Data Slice 0 programming completed... <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> DDR PHY Data Slice 1 programming in progress.. <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> DDR PHY Data Slice 1 programming completed... <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> DDR PHY Data Slice 2 programming in progress.. <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> DDR PHY Data Slice 2 programming completed... <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> DDR PHY Data Slice 3 programming in progress.. <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> DDR PHY Data Slice 3 programming completed... <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> DDR PHY Address slice 0 programming in progress.. <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> DDR PHY Address Slice 0 programming completed... <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> DDR PHY programming in progress.. <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> DDR PHY programming completed... <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> DDR PI initialization started... <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> DDR Controller initialization started... <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> Waiting for frequency change requests ... <<<---
DMSC_Cortex_M3_0: GEL Output: Frequency change request type 1 received from controller
DMSC_Cortex_M3_0: GEL Output: Setting DDR PLL + HSDIV to 933MHz
DMSC_Cortex_M3_0: GEL Output: DDR PLL Calibration Control MMR value: 0x80170000
DMSC_Cortex_M3_0: GEL Output: DDR PLL Calibration Control MMR value: 0x80000213
DMSC_Cortex_M3_0: GEL Output: DDR PLL + HSDIV set to 933MHz.
DMSC_Cortex_M3_0: GEL Output: Frequency change request type 0 received from controller
DMSC_Cortex_M3_0: GEL Output: Setting DDR PLL to 20MHz/19.2MHz on silicon (bypass)
DMSC_Cortex_M3_0: GEL Output: Set PLL to external bypass (20MHz/19.2MHz on SVB/EVM).
DMSC_Cortex_M3_0: GEL Output: Frequency change request type 1 received from controller
DMSC_Cortex_M3_0: GEL Output: Setting DDR PLL + HSDIV to 933MHz
DMSC_Cortex_M3_0: GEL Output: DDR PLL Calibration Control MMR value: 0x80170000
DMSC_Cortex_M3_0: GEL Output: DDR PLL Calibration Control MMR value: 0x8000021C
DMSC_Cortex_M3_0: GEL Output: DDR PLL + HSDIV set to 933MHz.
DMSC_Cortex_M3_0: GEL Output: Frequency change request type 0 received from controller
DMSC_Cortex_M3_0: GEL Output: Setting DDR PLL to 20MHz/19.2MHz on silicon (bypass)
DMSC_Cortex_M3_0: GEL Output: Set PLL to external bypass (20MHz/19.2MHz on SVB/EVM).
DMSC_Cortex_M3_0: GEL Output: Frequency change request type 1 received from controller
DMSC_Cortex_M3_0: GEL Output: Setting DDR PLL + HSDIV to 933MHz
DMSC_Cortex_M3_0: GEL Output: DDR PLL Calibration Control MMR value: 0x80170000
DMSC_Cortex_M3_0: GEL Output: DDR PLL Calibration Control MMR value: 0x80000209
DMSC_Cortex_M3_0: GEL Output: DDR PLL + HSDIV set to 933MHz.
DMSC_Cortex_M3_0: GEL Output: Frequency change request type 2 received from controller
DMSC_Cortex_M3_0: GEL Output: Setting DDR PLL + HSDIV to 933MHz
DMSC_Cortex_M3_0: GEL Output: DDR PLL Calibration Control MMR value: 0x80170000
DMSC_Cortex_M3_0: GEL Output: DDR PLL Calibration Control MMR value: 0x8000020F
DMSC_Cortex_M3_0: GEL Output: DDR PLL + HSDIV set to 933MHz.
DMSC_Cortex_M3_0: GEL Output: Frequency change request type 1 received from controller
DMSC_Cortex_M3_0: GEL Output: Setting DDR PLL + HSDIV to 933MHz
DMSC_Cortex_M3_0: GEL Output: DDR PLL Calibration Control MMR value: 0x80170000
DMSC_Cortex_M3_0: GEL Output: DDR PLL Calibration Control MMR value: 0x80000218
DMSC_Cortex_M3_0: GEL Output: DDR PLL + HSDIV set to 933MHz.
DMSC_Cortex_M3_0: GEL Output: Frequency change request type 2 received from controller
DMSC_Cortex_M3_0: GEL Output: Setting DDR PLL + HSDIV to 933MHz
DMSC_Cortex_M3_0: GEL Output: DDR PLL Calibration Control MMR value: 0x80170000
DMSC_Cortex_M3_0: GEL Output: DDR PLL Calibration Control MMR value: 0x8000020E
DMSC_Cortex_M3_0: GEL Output: DDR PLL + HSDIV set to 933MHz.
DMSC_Cortex_M3_0: GEL Output: Frequency change request type 1 received from controller
DMSC_Cortex_M3_0: GEL Output: Setting DDR PLL + HSDIV to 933MHz
DMSC_Cortex_M3_0: GEL Output: DDR PLL Calibration Control MMR value: 0x80170000
DMSC_Cortex_M3_0: GEL Output: DDR PLL Calibration Control MMR value: 0x80000213
DMSC_Cortex_M3_0: GEL Output: DDR PLL + HSDIV set to 933MHz.
DMSC_Cortex_M3_0: GEL Output: Frequency change request type 2 received from controller
DMSC_Cortex_M3_0: GEL Output: Setting DDR PLL + HSDIV to 933MHz
DMSC_Cortex_M3_0: GEL Output: DDR PLL Calibration Control MMR value: 0x80170000
DMSC_Cortex_M3_0: GEL Output: DDR PLL Calibration Control MMR value: 0x80000211
DMSC_Cortex_M3_0: GEL Output: DDR PLL + HSDIV set to 933MHz.
DMSC_Cortex_M3_0: GEL Output: --->>> All frequency change requests have completed... <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> LPDDR4 Initialization is DONE! <<<---

Thank you

Vijender

0 Prasad Jondhale over 6 years ago in reply to Vijender Saini

TI__Mastermind 27743 points

Hello Vijender,

There are two UART ports on MCU UART. Believe you have connected MCU UART1 which is for SysFW Terminal.

Please use MCU UART0 for getting app logs.

Regards,

Prasad

Code Composer Studio™︎

Code Composer Studio forum

CCS/PROCESSOR-SDK-DRA8X-TDA4X: Ethernet Loop Back Test on TDA4x hangs on the Bios_start()