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CCS/TMS320F28377D: complier warning 10462

Part Number: TMS320F28377D

Tool/software: Code Composer Studio

I'm having a similar problem as shown below.

https://e2e.ti.com/support/tools/ccs/f/81/t/897582 

 mentioned that "You can safely ignore this warning if you can confirm that the C code data access of the CLA defined data are both accessing the same memory location".

My question is how to confirm the above access are in the same memory location.

In my project, several global variables are defined in CLA located in RAMLS5. CLA code which run in RAMLS2~RAMLS4 and C code which run in RAMGSx or FLASH will access these global variables.

So far, the project works well. But I'm not sure if there is any potential problem.

  • In most cases, the best answer is to defined the shared data variables in the C28x code, and not the CLA code.  For more details, please search the C28x compiler manual for the sub-chapter titled Variables and Data Types.

    Thanks and regards,

    -George

  • The compiler warning 10462 is added in CGT 20.2.0.LTS. Then if I use the older version of CGT , the blocking issue is not exist? OR, no matter which version of the CGT used, the potential risk is always exist?

    The complier manual adds the related information since SPRU514S.

  • The blocking issue is not new and it exists in all older compiler versions. The issue arises because the way data pages work on each device does not match.  C28 code blocks data while CLA code does not.

    The diagnostic was added because of the blocking issue, and the fact that these types of errors are runtime and difficult to debug and pin point.

    Thanks

    Greg

  • The c28x compiler maunal mentions information as shown below:

    As I don't use -plink option, so the removing reduant DP loads isn't active. Does this mean the blocking issue doesn't exsit?

  • The blocking issue still exists. And the best practice of defining shared variables in C28 code is still relevant.

    Blocking is done for C28 global data during code generation and is unrelated to the post-link optimization tool.

    For Data Page details see spru514t: Section 3.11 "Data Page Pointer load optimization"

    For data blocking details please see:
    https://e2e.ti.com/blogs_/archives/b/toolsinsider/archive/2016/11/17/data-blocking-in-the-c2000-mcu-compiler-explained 

    Data page blocking is done so that the compiler can remove redundant DP loads, however this is done during code generation and does not require/depend-on the post-linker tool.

    The post-link tool is separate from above and one of it's optimizations involves attempting to remove even more redundant DP loads.

    Regards,
    Greg