Tool/software: TI C/C++ Compiler
CDCE62005 VHDL configuration code
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Tool/software: TI C/C++ Compiler
CDCE62005 VHDL configuration code
Hi,
Can you clarify what specific issue you try to resolve here? Are you looking for "There is some SPI-specific VHDL code floating around for the FPGA on the C6678 demo board that you can use as a template. It was made available to us even though we were designing around the C6657. If you have trouble tracking it down, I'm sure someone at TI can help you out."?
Regards, Eric
Hi,
The example FPGA code can be downloaded from the Einfochips website. The clock_spi2x.v and clock_spi3x.v files contain the register values programmed into the clock generators. The spi3x.v is a carryover from the C6678 EVM and is not used for the C6657 EVM. The spi2x.v file contains the following verilog code.
else if (PLL_Lock2 & (write_recd!=Write_data) ) begin
case (Write_data[3:0])
4'd0:blk_mem_Write_data<=Write_data; //E984_0320
4'd1:blk_mem_Write_data<=Write_data; //6984_0301
4'd2:blk_mem_Write_data<=Write_data; //E902_0302
4'd3:blk_mem_Write_data<=Write_data; //E984_0303
4'd4:blk_mem_Write_data<=Write_data; //6986_0314
4'd5:blk_mem_Write_data<=Write_data; //101C_0BE5
4'd6:blk_mem_Write_data<=Write_data; //04BE_0F06
4'd7:blk_mem_Write_data<=Write_data; //FD00_37F7
default:begin end //0000008e
endcase
These are the register value programmed into the CDCE62005 taken from the saved file from the CDCE programming tool.
Regards, Bill