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CCS/PROCESSOR-SDK-DRA8X-TDA4X: PReLU WARNING of model import

shuai wang32
Genius 4770 points
Part Number: PROCESSOR-SDK-DRA8X-TDA4X


Tool/software: Code Composer Studio

HI:

            I   am   using    psdk_rtos_auto_j7_06_02_00_21   SDK ,         for  TIDL       i     have   try      some    example   model  in  the     TIDL Importer    document.

           but    i      Import    my   CNN    have   some   problem.    log  lis  like   follow!

          

WARNING: PReLU Layer fc256_relu's bias cannot be found(or not match) in coef file, Random bias will be generated! Only for evaluation usage! Results are all random!

IPLayer,=256

           in   my  cnn    have     many   PReLU Layer   ,   i  found    PReLU Layer  after    FlattenLayer   have    this   WARNING:      i   check   the   code    

int32_t dataSize = TIDLPCLayers.layerParams.batchNormParams.numChannels   is   PReLU Layer   is  1,    

          so     i  donot   know   how   do  you   slove     PReLU Layer    after    FlattenLayer?      

Thanks!

Shuai

         

     

  • 0
    Genius 4770 points

    Hi  :

              import    have   this   log ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~

    Processing config file #0 : /home/super/psdk_rtos_auto_j7_06_02_00_21/tidl_j7_01_01_00_10/ti_dl/utils/tidlModelImport/tempDir/qunat_stats_config.txt
     ----------------------- TIDL Process with REF_ONLY FLOW ------------------------

    #    0 . .. T       2.65  ... .... .....
    ------------------ Network Compiler Traces -----------------------------
    Main iteration numer: 0....

     Life time alive buffers are with ID: 10034 ( 0), 50033 ( 1), 60033 ( 1), 40002 ( 2), 20034 ( 0), 33 ( 2), 40001 ( 2),
    Preparing for memory allocation : internal iteration number: 0
    Mmeory overlap issue, dataId = 6, baseAddrconstSatisfied = -1
    Main iteration numer: 1....

     Life time alive buffers are with ID: 10034 ( 0), 50033 ( 1), 60033 ( 1), 40002 ( 2), 20034 ( 0), 33 ( 2), 40001 ( 2),
    Preparing for memory allocation : internal iteration number: 0
    successful Memory allocation

    -------------------- Network Compiler : Analysis Results are available --------------------

    ****************************************************
    **                ALL MODEL CHECK PASSED          **
    ****************************************************
     Thanks!

    Shuai

            

  • 0 in reply to shuai wang32
    Genius 4770 points

    Hi :

            i     set     debugTraceLevel = 3    writeTraceLevel = 3

            in      psdk_rtos_auto_j7_06_02_00_21/tidl_j7_01_01_00_10/ti_dl/test/trace$  

           float.bin   of   second    layer  is  like   follow,    i   think   it   not  ringt,      and   i   set   

    inMean = 128.0 128.0 128.0
    inScale = 0.00390625 0.00390625 0.00390625

      (   float.bin   of   second    layer)    -383.07528 -132.09492 -132.09492 -118.88542 -118.88542 -118.88542 -105.67594   

    then    i   change   

    inMean = 0.0 0.0 0.0
    inScale = 0.0 0.0 0.0

    float.bin   of   second    layer    is  not  change     all layer  float.bin    is   not  change   ,  so   i  think   its   very strange.

    Thanks!

    Shuai

     

  • 0 in reply to shuai wang32
    TI__Mastermind 22145 points

    Could you please share model and config files to reproduce this issue.

    Need not to be the same model, A representative model where the issue could be reproduced is enough 

  • 0 in reply to shuai wang32
    Genius 4770 points

    Hi   :

          test_simple1      is    the   model !

         test.jpg      is  the   image

       tidl_import_test    and  tidl_infer_test   are  my   config  

       log_of_tidl_model_import  and   logof_PC_dsp_test_dl_algo.out   are  my  logs

       trace   is  layer  dumps

    Thanks!

    Shuai