Part Number: TCI6638K2K
Tool/software: Code Composer Studio
Hello, TI engineers:
When we use C6638 and FPGA K7 to communicate, FPGA USES SWRITE and NREAD,
(1) When NREAD alone reads the data of C6638 DDR, it is about 40000CLK. Note: CLK is the time from sending read command request to getting read packet captured by FPGA.
(2) Add SWRITE to write data, and the corresponding CLK will reach 120000CLK. Is there a delay in responding to read packets when adding read request to write data?