Other Parts Discussed in Thread: RM48L952, , HALCOGEN
Tool/software: TI C/C++ Compiler
Is the armobjdump utility from ti-cgt-arm_20.2.1.LTS supposed to be able to generate correct disassembly?
Trying on some big and little endian out files shows incorrect disassembly.
1. armobjdump -d --source for a little-endian RM48L952 program produced:
Disassembly of section .text:
00000280 <systemInit>:
; {
280: f8 40 2d e9 push {r3, r4, r5, r6, r7, lr}
; systemREG1->CSDISSET = 0x00000002U | 0x00000040U;
284: d1 4f 0e e3 <unknown>
288: 42 c0 a0 e3 mov r12, #66
28c: ff 4f 4f e3 <unknown>
290: ed 5f 0e e3 <unknown>
294: ff 5f 4f e3 <unknown>
298: 63 cf 84 e5 str r12, [r4, #3939]
; while((systemREG1->CSDIS & 0x42U) != 0x42U)
29c: 5f cf 94 e5 ldr r12, [r4, #3935]
2a0: 42 c0 0c e2 and r12, r12, #66
2a4: 42 00 5c e3 cmp r12, #66
2a8: 5f cf 94 15 ldrne r12, [r4, #3935]
2ac: 03 00 00 0a beq #12 <$C$L2>
Which has some instructions as <unknown>. Whereas the output from gcc-arm-none-eabi-7-2017-q4-major/bin/arm-none-eabi-objdump -d --source was:
Disassembly of section .text:
00000280 <systemInit>:
/* SourceId : SYSTEM_SourceId_006 */
/* DesignId : SYSTEM_DesignId_006 */
/* Requirements : HL_SR471 */
void systemInit(void)
{
280: e92d40f8 push {r3, r4, r5, r6, r7, lr}
systemREG1->CSDISSET = 0x00000002U | 0x00000040U;
284: e30e4fd1 movw r4, #61393 ; 0xefd1
288: e3a0c042 mov ip, #66 ; 0x42
28c: e34f4fff movt r4, #65535 ; 0xffff
290: e30e5fed movw r5, #61421 ; 0xefed
294: e34f5fff movt r5, #65535 ; 0xffff
298: e584cf63 str ip, [r4, #3939] ; 0xf63
while((systemREG1->CSDIS & 0x42U) != 0x42U)
29c: e594cf5f ldr ip, [r4, #3935] ; 0xf5f
2a0: e20cc042 and ip, ip, #66 ; 0x42
2a4: e35c0042 cmp ip, #66 ; 0x42
2a8: 1594cf5f ldrne ip, [r4, #3935] ; 0xf5f
2ac: 0a000003 beq 2c0 <systemInit+0x40>
2. armobjdump -d --source for a for a big-endian TMS570LC4357 program produced:
Disassembly of section .text:
00000020 <adcInit>:
; adcREG1->RSTCR = 1U;
20: e5 9f 0a 7c <unknown>
24: e3 a0 c0 01 biceq r10, r0, r3, ror #1
28: e5 80 c0 00 sbceq r8, r0, r5, ror #1
; adcREG1->RSTCR = 0U;
2c: e5 9f 0a 70 andvc r9, r10, r5, ror #31
30: e3 a0 c0 00 sbceq r10, r0, r3, ror #1
34: e5 80 c0 00 sbceq r8, r0, r5, ror #1
; adcREG1->OPMODECR |= 0x80000000U;
38: e5 9f 0a 68 stmdavs r10, {r0, r2, r5, r6, r7, r8, r9, r10, r11, r12, pc}
3c: e5 90 c0 00 sbceq r9, r0, r5, ror #1
40: e3 8c c1 02 sbceq r8, r1, #58112
44: e5 80 c0 00 sbceq r8, r0, r5, ror #1
; adcREG1->CLOCKCR = 7U;
48: e5 9f 0a 5c <unknown>
4c: e3 a0 c0 07 strbeq r10, [r0, r3, ror #1]
50: e5 80 c0 00 sbceq r8, r0, r5, ror #1
Which has some instructions as <unknown> and others which don't make sense. Whereas the output from gcc-arm-none-eabi-7-2017-q4-major/bin/arm-none-eabi-objdump -d --source was:
Disassembly of section .text:
00000020 <adcInit>:
/* USER CODE END */
/** @b Initialize @b ADC1: */
/** - Reset ADC module */
adcREG1->RSTCR = 1U;
20: e59f0a7c ldr r0, [pc, #2684] ; aa4 <adc1GetConfigValue+0x200>
24: e3a0c001 mov ip, #1
28: e580c000 str ip, [r0]
adcREG1->RSTCR = 0U;
2c: e59f0a70 ldr r0, [pc, #2672] ; aa4 <adc1GetConfigValue+0x200>
30: e3a0c000 mov ip, #0
34: e580c000 str ip, [r0]
/** - Enable 12-BIT ADC */
adcREG1->OPMODECR |= 0x80000000U;
38: e59f0a68 ldr r0, [pc, #2664] ; aa8 <adc1GetConfigValue+0x204>
3c: e590c000 ldr ip, [r0]
40: e38cc102 orr ip, ip, #-2147483648 ; 0x80000000
44: e580c000 str ip, [r0]
