This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Compiler: DS90UB960 two csi port select

Tool/software: TI C/C++ Compiler

Hi  teams

Recently,we are using the 960+953+4 sensors.The sensor output is the same pixel  1920*1080.

But the cpu csi2 side is not meeting demand,the up side is 2.5Gbps。We plan use 960 two ports output data to  two csi2 of cpu.

sensorA----------|   -------------960 csi2 port 0

sensorB----------|

sensorC----------|--------------960 csi2 port 1

sensorD----------|

How should I setting the regs flow of DS90UB960  ?

BRs

thanks

  • Good afternoon,

    I am working on an answer to your question and will get back to you tomorrow.

    Regards,

    Carrie

  • OK, thanks

    hope for your reply

  • Good afternoon,

    Each CSI-2 output port has 4 data lanes, each of which can support up to 1.6 Gbps. Therefore, each port can support 1.6*4 = 6.4 Gbps bandwidth. With 2 sensors per port (totaling 4 sensors for 2 ports), each sensor has 3.2 Gbps of available bandwidth.

    To program the DS90UB960 to support your configuration (A  and B -> TX0, C and D -> TX1), set these register values:

    Set the virtual channel ID of each port in the CSI_VC_MAP register (Address 0x72). For example, a value of 0xE4 would assign a VC-ID of 0 to RX0, 1 to RX1, 2 to RX2, and 3 to RX3.

    Enable port forwarding and map the RX ports to the CSI-2 ports in the FWD_CTL1 register (Address 0x20). For example, a value of 0x0C enables forwarding for all RX ports and sets RX0/RX1 to TX0, and RX2/RX3 to TX1. It is recommended to disable forwarding for a port before changing its mapping.

    Also make sure to set CSI-2 Transmit enable (and Continuous clock if desired) in CSI_ CTL register 2. Enable CSI-2 Periodic Calibration (if desired) in the CSI_CTL2 register.

    Regards,

    Carrie

  • thanks Carrie 

    this is helpful to me.