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CCS/RM57L843: Interfacing SRAM (Asynchronous Memory) with RM57 Micro-controller - Reg. Linker File Editing

Part Number: RM57L843

Tool/software: Code Composer Studio

Hi!

I am interfacing a SRAM device (512K X 16 bit) with RM57 micro-controller. The SRAM as you might know is an Asynchronous memory. I have used EMIF module to carry out this functionality. I am using chip select 4 of EMIF as the chip select for SRAM.

Basically, my question is regarding linker file updations, that I'll have to do; to map the CS4 memory of the controller into SRAM memory. I am a beginner when it comes to the concept of linker files and therefore I want to know what necessary changes have to be done (additions or deletions) in the linker file to support the SRAM accessing.

A snippet of code as an example would be really very helpful.

Regards,

Chetan.

  • Hello Chetan,

    Here is an example of linker command which includes SDRAM in memory directive, and a section allocated in SDRAM. The link at the bottom is a nice link for understanding the linker cmd file:

    /* Memory Map */

    MEMORY
    {
    /* USER CODE BEGIN (2) */
    /* USER CODE END */
    VECTORS (X) : origin=0x00000000 length=0x00000020
    FLASH0 (RX) : origin=0x00000020 length=0x001FFFE0
    FLASH1 (RX) : origin=0x00200000 length=0x00200000
    STACKS (RW) : origin=0x08000000 length=0x00001500
    RAM (RW) : origin=0x08001500 length=0x0007EB00

    /* USER CODE BEGIN (3) */
    SDRAM (RWX) : origin=0x80000000 length=0200000000
    /* USER CODE END */
    }

    /* USER CODE BEGIN (4) */
    /* USER CODE END */


    /*----------------------------------------------------------------------------*/
    /* Section Configuration */

    SECTIONS
    {
    /* USER CODE BEGIN (5) */
    /* USER CODE END */
    .intvecs : {} > VECTORS
    .text align(32) : {} > FLASH0 | FLASH1
    .const align(32) : {} > FLASH0 | FLASH1
    .cinit align(32) : {} > FLASH0 | FLASH1
    .pinit align(32) : {} > FLASH0 | FLASH1
    .bss : {} > RAM
    .data : {} > RAM
    .sysmem : {} > RAM

    /* USER CODE BEGIN (6) */
    .telem : {} > SDRAM
    /* USER CODE END */
    }

    /* USER CODE BEGIN (7) */
    /* USER CODE END */

    http://software-dl.ti.com/ccs/esd/documents/sdto_cgt_Linker-Command-File-Primer.html

  • Dear Wang,

    Thanks for the reply! I did go through that site earlier and it has given me some understanding of the directives.

    In your example above, you used the ".telem" as your output section for all the code or data mapped into SDRAM memory region, right? (As per what it says in the link you shared).

    Lastly, in the application code, using a pragma like:

    #pragma DATA_SECTION DATA(".telem")

    uint32 Temp;

    uint8 uc_cnt;

    #pragma DATA_SECTION DEFAULT

    would mean that the variables "Temp" and "uc_cnt" be mapped into SDRAM right? Is the understanding correct? Same applies to the pragma CODE_SECTION too, right?

    Regards,

    Chetan.

  • The syntax of the pragma in C is:

    #pragma DATA_SECTION ( abc , "myDATA_section" );

    uint32_t abc;

    The syntax of the pragma in C++ is: 

    #pragma DATA_SECTION ( "myDATA_section" );

    uint32_t abc;

    #pragma CODE_SECTION (fn, "my_sect")

    int fn(int x) {

       return x;

    }

    #pragma SET_CODE_SECTION(".blinky_section")

    void blinky()
    {
           int i;
           gioSetDirection(hetPORT1, 1);
           while(1)
           {
                 gioToggleBit(hetPORT1, 0);
                 for(i=0;i<1000000;i++);
            }
    }

    #pragma SET_CODE_SECTION()

    The DATA_SECTION pragma and CODE_SECTION pragma are described in the Compiler User's Guide.