Compiler/LMK04208: LMK04828

Hello Uzmeed,

Do you already have a configuration for this device?  Assuming you have programmed a VCO frequency of 3000 MHz, then the only field that needs to be re-programmed is the clock divider.  For example, if CLKout0 = 150 MHz from a 3000 MHz VCO, then CLKout0_DIV in register R0[15:5] must be set = 20.

• To change to 100 MHz for example, simply re-program CLKout0_DIV = 30.
• To change to 50 MHz for example, simply re-program CLKout0_DIV = 60.

Anytime you change the divider, it is possible for the phase of the output clock to change with respect to the other clocks.  If required you can re-SYNC the output dividers.

• To change to 70 MHz, using a VCO of 3000 MHz is no longer workable as there is no integer division from 3000 MHz to 70 MHz.  To produce this output frequency, you must program the PLL R and PLL N dividers to produce a new VCO frequency which is evenly divisible by 70 MHz.
• Please refer to datasheet section 9.1.5 for info on PLL programming, note the example in section 9.1.5.1.