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CCS/TMS320F28377D: FLASH Memory Management Please help !!!!

Peter Adamcik
Expert 1425 points

Part Number: TMS320F28377D

Tool/software: Code Composer Studio

Hi Guys, I'm an assembler programmer using the F28377D. CCS9 assembles my code to the F28377D to FLASHB which is only 8k in size, this is ok no probs.

My assembler program has now increased greater that 8k, CCS9 then assembles the code to FLASHE which is 32k.

My assembler code now is greater than 32k and CCS9 now says my code will not fit into any of the 32k flash banks and now won't assemble my code. My F28377D has 1024k of flash.

I need to tell CCS9 to write my code STARTING from FLASHA and then when FLASHA is full to continue to write the rest of the code into FLASHB and continue to FLASHN.

I remember doing this years ago with CCS6 I think but just can't remember how I did it. Please let me know how assign the flash banks. Linear I think its called but not sure.

Thanks guys and waiting for your reply. 

Peter :)

  • 0
    TI__Mastermind 27875 points

    Peter,

    If your linker command file has memory assignments like this

    FLASH_BANK0_SEC4 : origin = 0x084000, length = 0x001000 /* on-chip Flash */
    FLASH_BANK0_SEC5 : origin = 0x085000, length = 0x001000 /* on-chip Flash */
    FLASH_BANK0_SEC6 : origin = 0x086000, length = 0x001000 /* on-chip Flash */

    under SECTIONS, you can specify something like this (essentially a logical OR operation)

    .text            : >>FLASH_BANK0_SEC4 | FLASH_BANK0_SEC5 | FLASH_BANK0_SEC6,   PAGE = 0, ALIGN(4)

    Just modify the above logic to suit your needs.

    Thanks,

    Sira

  • 0 in reply to Sira Rao80
    Expert 1425 points

    Thank you Sira, I'll check it out. Have a great day.

    Peter :) 

  • 0 in reply to Sira Rao80
    Expert 1425 points

    Hi Sira, still does not work even after I changed the .text info. Below is what I change it to.

    I need to store a picture in FLASH memory and the size of the picture is 128k. The linker only allows me to write into FLASHE which is 32k and then errors saying program will not fit in to the allocated memory.

    In the code below I've told it to start writing my .text cose from FLASHA and continue to FLASHB and then FLASH C until FLASHN.

    Oh, my startup code is in C and then calls my assembly file and that is where my picture .word data is.

    Please let me know how to fix it. I will need to use the whole 1MB of FLASH memory. I can not divide my pictures in different sections, it does not work that way.

    Thanks Sira.

    SECTIONS

    {

       /* Allocate program areas: */

       .cinit              : > FLASHA      PAGE = 0, ALIGN(4)

       .pinit              : > FLASHA,     PAGE = 0, ALIGN(4)

       .text               : >> FLASHA | FLASHB | FLASHC | FLASHD | FLASHE | FLASHF | FLASHG | FLASHH | FLASHI | FLASHJ | FLASHK | FLASHL | FLASHM | FLASHN, PAGE = 0, ALIGN(4)

       codestart           : > BEGIN       PAGE = 0, ALIGN(4)

  • 0 in reply to Peter Adamcik
    TI__Mastermind 27875 points

    Peter,

    I am wondering why the linker is allowing you to write the image only in FlashE. What's in FlashA/B/C/D?

    Can you send me your linker cmd file?

    Thanks,

    Sira

  • 0 in reply to Sira Rao80
    Expert 1425 points

    Hi Sira, thank you for your help.  My problem is that the linker splits up my 24bit picture data and stores it in all the FLASH banks and not in one linear memory location. My picture data is about 150k in size. I can't have it store parts of the picture in all of the FLASH banks. Because my picture data is large the linker tries to store it in the largest FLASH bank I have with is 32k and then it fails and my assembler program will not build.

    What is stored in FLASHA to FLASHD is other parts or my assembler code AND ( PARTS ) of my 24bit picture. 

    Below is my linker file. Can you rewrite it so the linker downloads my code to START from FLASHA and FINISH at FLASHN and Not to split my code in different FLASH banks.

    Here is my CCS9.3.0 Linker code:

    MEMORY

    {

    PAGE 0 :  /* Program Memory */

              /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */

              /* BEGIN is used for the "boot to Flash" bootloader mode   */

       BEGIN           : origin = 0x080000, length = 0x000002

       RAMM0           : origin = 0x000122, length = 0x0002DE

       RAMD0           : origin = 0x00B000, length = 0x000800

       RAMLS0          : origin = 0x008000, length = 0x000800

       RAMLS1          : origin = 0x008800, length = 0x000800

       RAMLS2      : origin = 0x009000, length = 0x000800

       RAMLS3      : origin = 0x009800, length = 0x000800

       RAMLS4      : origin = 0x00A000, length = 0x000800

       RAMGS14          : origin = 0x01A000, length = 0x001000

       RAMGS15          : origin = 0x01B000, length = 0x001000

       RESET           : origin = 0x3FFFC0, length = 0x000002

       

       /* Flash sectors */

       FLASHA           : origin = 0x080002, length = 0x001FFE /* on-chip Flash */

       FLASHB           : origin = 0x082000, length = 0x002000 /* on-chip Flash */

       FLASHC           : origin = 0x084000, length = 0x002000 /* on-chip Flash */

       FLASHD           : origin = 0x086000, length = 0x002000 /* on-chip Flash */

       FLASHE           : origin = 0x088000, length = 0x008000 /* on-chip Flash */

       FLASHF           : origin = 0x090000, length = 0x008000 /* on-chip Flash */

       FLASHG           : origin = 0x098000, length = 0x008000 /* on-chip Flash */

       FLASHH           : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */

       FLASHI           : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */

       FLASHJ           : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */

       FLASHK           : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */

       FLASHL           : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */

       FLASHM           : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */

       FLASHN           : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */   

    PAGE 1 : /* Data Memory */

             /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */

       BOOT_RSVD       : origin = 0x000002, length = 0x000120     /* Part of M0, BOOT rom will use this for stack */

       RAMM1           : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */

       RAMD1           : origin = 0x00B800, length = 0x000800

       RAMLS5      : origin = 0x00A800, length = 0x000800

       RAMGS0      : origin = 0x00C000, length = 0x001000

       RAMGS1      : origin = 0x00D000, length = 0x001000

       RAMGS2      : origin = 0x00E000, length = 0x001000

       RAMGS3      : origin = 0x00F000, length = 0x001000

       RAMGS4      : origin = 0x010000, length = 0x001000

       RAMGS5      : origin = 0x011000, length = 0x001000

       RAMGS6      : origin = 0x012000, length = 0x001000

       RAMGS7      : origin = 0x013000, length = 0x001000

       RAMGS8      : origin = 0x014000, length = 0x001000

       RAMGS9      : origin = 0x015000, length = 0x001000

       RAMGS10     : origin = 0x016000, length = 0x001000

       RAMGS11     : origin = 0x017000, length = 0x001000

       RAMGS12     : origin = 0x018000, length = 0x001000

       RAMGS13     : origin = 0x019000, length = 0x001000

       

       CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400

       CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400

    }

    SECTIONS

    {

       /* Allocate program areas: */

       .cinit              : > FLASHA      PAGE = 0, ALIGN(4)

       .pinit              : > FLASHA,     PAGE = 0, ALIGN(4)

       .text               : >> FLASHA | FLASHB | FLASHC | FLASHD | FLASHE | FLASHF | FLASHG | FLASHH | FLASHI | FLASHJ | FLASHK | FLASHL | FLASHM | FLASHN, PAGE = 0, ALIGN(4)

       codestart           : > BEGIN       PAGE = 0, ALIGN(4)

    #ifdef __TI_COMPILER_VERSION__

       #if __TI_COMPILER_VERSION__ >= 15009000

        .TI.ramfunc : {} LOAD = FLASHD,

                             RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,

                             LOAD_START(_RamfuncsLoadStart),

                             LOAD_SIZE(_RamfuncsLoadSize),

                             LOAD_END(_RamfuncsLoadEnd),

                             RUN_START(_RamfuncsRunStart),

                             RUN_SIZE(_RamfuncsRunSize),

                             RUN_END(_RamfuncsRunEnd),

                             PAGE = 0, ALIGN(4)

       #else

       ramfuncs            : LOAD = FLASHD,

                             RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,

                             LOAD_START(_RamfuncsLoadStart),

                             LOAD_SIZE(_RamfuncsLoadSize),

                             LOAD_END(_RamfuncsLoadEnd),

                             RUN_START(_RamfuncsRunStart),

                             RUN_SIZE(_RamfuncsRunSize),

                             RUN_END(_RamfuncsRunEnd),

                             PAGE = 0, ALIGN(4)   

       #endif

    #endif

     

       /* Allocate uninitalized data sections: */

       .stack              : > RAMM1        PAGE = 1

       .ebss               : >> RAMLS5 | RAMGS0 | RAMGS1       PAGE = 1

       .esysmem            : > RAMLS5       PAGE = 1

       /* Initalized sections go in Flash */

       /*.econst             : >> FLASHF | FLASHG | FLASHH      PAGE = 0, ALIGN(4)

       .switch             : > FLASHB      PAGE = 0, ALIGN(4)

       */

       .reset              : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */

       Filter_RegsFile     : > RAMGS0,   PAGE = 1

       

       SHARERAMGS0 : > RAMGS0, PAGE = 1

       SHARERAMGS1 : > RAMGS1, PAGE = 1

       

       /* The following section definitions are required when using the IPC API Drivers */ 

        GROUP : > CPU1TOCPU2RAM, PAGE = 1 

        {

            PUTBUFFER 

            PUTWRITEIDX 

            GETREADIDX 

        }

        

        GROUP : > CPU2TOCPU1RAM, PAGE = 1

        {

            GETBUFFER :    TYPE = DSECT

            GETWRITEIDX :  TYPE = DSECT

            PUTREADIDX :   TYPE = DSECT

        }  

        

    }

    /*

    //===========================================================================

    // End of file.

    //===========================================================================

    */

    Thanks Sira, hope to hear from you soon.

    Peter

  • 0 in reply to Peter Adamcik
    TI__Guru* 93800 points

    Peter,

    If I understand, the picture is part of the .text section.  I would suggest putting it into its own section so you have better control over its placement. 

    Then in the MEMORY section create a flash region that is big enough for the image by combining flash sectors.  i.e instead of defining FLASHA and FLASHB, FLASHC.. define FLASH_ABC (or whatever you like to name it) with the combined start/length.  This doesn't change the physical layout of the flash so you will still only be able to erase a sector minimum, but it does allow the linker to see it as one big chunk of memory.

    Then in the SECTIONS allocate the section with the image to this flash MEMORY region.

    Regards

    Lori