Compiler/AM5726: OCMC_RAM1,2,3 Sharing between two cores

Vadim Malinovsky

Part Number: AM5726

Tool/software: TI C/C++ Compiler

If i have 2 cores for example (A15_0 and DSP1), in cfg of A15_0 Program.sectMap["heapMemSlowSection"].loadSegment = "OCMC_RAM1" and in platform package of DSP1 i have

Is OCMC_RAM is per core or it is common ram for all cores and i need carefully assign it by adresses between cores so there is no overlaps? Thanks.

over 5 years ago

0 Stanley Liu over 5 years ago

TI__Guru 50045 points

OCMC RAM is on L3 interconnect and shared by all cores.

Regards,
Stanley

0 Vadim Malinovsky over 5 years ago in reply to Stanley Liu

Intellectual 320 points

Thanks, the next question is there is a recommended way to manage memory assignments in app.cfg + RTSC for multiple cores so there is only on point of change and no overlaps?

Thanks,

Vadim

0 Stanley Liu over 5 years ago in reply to Vadim Malinovsky

TI__Guru 50045 points

There is no specific way to do this.

We just partition the memory statically and each core use a different section of the memory.

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Compiler/AM5726: OCMC_RAM1,2,3 Sharing between two cores