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CCS/RM57L843: mibspi ISR implementation

Part Number: RM57L843
Other Parts Discussed in Thread: HALCOGEN,

Tool/software: Code Composer Studio

Hello,

I'm new to CCS and Halcogen, I've configured mibspi1 in halcogen and enabled groupnotification . I want to write code in interrupt service routine , I'm not able to understand how to add ISR functions to code (in .c file). Kindly help on this point. Also how to identify source of interrupt (whether interrupt is for transfer / receive / parrity error).

  • Hello Tukaram,

    1. If the VIM channel for MibSPI1 (channel 12, or channel 26) is checked, the HALCOGen will generate the MibSPI1 ISR automatically. There are two interrupt lines, one each for Level 0 (or High level)  and Level 1 (or low level). Level 0 has higher priority than level 1. 

    2. Select the interrupt level (high or low) for MibSPI TX and RX interrupt:

    3. The ISR generated by HALCOGen is located at the end of mibspi.c

    4. In multi-buffered mode (mibspi), there are 4 interrupts. They are enabled in TGINTENA register. Level 0 interrupt uses INTVECT0,a nd Level 1 interrupt uses the INTVECT1.

    • Transmission error interrupt
    • Receive overrun interrupt
    • TG suspended interrupt
    • TG completed interrupt

    The ((vec & 0x3FU) >> 1U) - 1U in mibspiGroupNotification(...) is the transfer group number 

  • Hello QJ Wang,

    Thank you for your reply . I've configured mibspi3 (mibspiREG3) as per your suggestion , still function "mibspiGroupNotification" not getting executed. below are snapshot for interrupt configurations:

    1) Interrupt selection -> High Level

    2) Data length and clock setting .

    3) Transfer group 0 setting

    4) Interrupt Setting 

    5) Code flow 

    I'm not able to understand which setting I've missed . Kindly guide on the same .

    Part no : RM57L843

    Thank you.

  • Please enable TG0 notification:

    mibspiEnableGroupNotification(mibspiREG3,0,0);