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Compiler/ARM-CGT: SDSCM00008685 Additional Information

PauloP
Prodigy 240 points

Part Number: ARM-CGT

Tool/software: TI C/C++ Compiler

The defect report states: 'var1' and 'var2' are shown to be in single registers

In order that I can better understand the implication of this defect I would appreciate additional information, specifically details of the test case which includes 'var1' and 'var2'.

  • 0
    Prodigy 240 points

    I put a simple test case of my own together and I can't see the issue that the defect refers to.

    Disassembly:

    141       {

              TestDefect():

    0000561c:   E92D407F            push       {r0, r1, r2, r3, r4, r5, r6, r14}

    142           unsigned long long var1 = 0xa9a9a9a956565656LL;

    00005620:   E28FCF5D            add        r12, pc, #0x174

    00005624:   E89C000C            ldm        r12, {r2, r3}

    00005628:   E88D000C            stm        r13, {r2, r3}

    143           unsigned long long var2 = 1LL;

    0000562c:   E28DC008            add        r12, r13, #8

    00005630:   E3A02000            mov        r2, #0

    00005634:   E3A03001            mov        r3, #1

    00005638:   E88C000C            stm        r12, {r2, r3}

    145           var1 = var1 + var2;

    0000563c:   E28DC008            add        r12, r13, #8

    00005640:   E89D0018            ldm        r13, {r3, r4}

    00005644:   E89C0060            ldm        r12, {r5, r6}

    00005648:   E0962004            adds       r2, r6, r4

    0000564c:   E0A51003            adc        r1, r5, r3

    00005650:   E88D0006            stm        r13, {r1, r2}

    147           var1 = var1 + 2LL;

    00005654:   E89D000C            ldm        r13, {r2, r3}

    00005658:   E3A0C000            mov        r12, #0

    0000565c:   E3A01002            mov        r1, #2

    00005660:   E0911003            adds       r1, r1, r3

    00005664:   E0AC0002            adc        r0, r12, r2

    00005668:   E88D0003            stm        r13, {r0, r1}

    148       }

    .asm

    TestDefect:

    ;* --------------------------------------------------------------------------*

                    .dwcfi    cfa_offset, 0

           STMFD     SP!, {A1, A2, A3, A4, V1, V2, V3, LR} ; [DPU_V7R4_PIPE0]

                    .dwcfi    cfa_offset, 32

                    .dwcfi    save_reg_to_mem, 14, -4

                    .dwcfi    save_reg_to_mem, 6, -8

                    .dwcfi    save_reg_to_mem, 5, -12

                    .dwcfi    save_reg_to_mem, 4, -16

                    .dwcfi    save_reg_to_mem, 3, -20

                    .dwcfi    save_reg_to_mem, 2, -24

                    .dwcfi    save_reg_to_mem, 1, -28

                    .dwcfi    save_reg_to_mem, 0, -32

    $C$DW$29          .dwtag DW_TAG_variable

                    .dwattr $C$DW$29, DW_AT_name("var1")

                    .dwattr $C$DW$29, DW_AT_TI_symbol_name("var1")

                    .dwattr $C$DW$29, DW_AT_type(*$C$DW$T$15)

                    .dwattr $C$DW$29, DW_AT_location[DW_OP_breg13 0]

     

    $C$DW$30          .dwtag DW_TAG_variable

                    .dwattr $C$DW$30, DW_AT_name("var2")

                    .dwattr $C$DW$30, DW_AT_TI_symbol_name("var2")

                    .dwattr $C$DW$30, DW_AT_type(*$C$DW$T$15)

                    .dwattr $C$DW$30, DW_AT_location[DW_OP_breg13 8]

     

                    .dwpsn file "../main.c",line 142,column 29,is_stmt,isa 2

           ADR       V9, $C$LL1           ; [DPU_V7R4_PIPE0] |142|

           LDMIA     V9, {A4,A3}           ; [DPU_V7R4_PIPE0] |142|

           STMIA     SP, {A4,A3}           ; [DPU_V7R4_PIPE0] |142|

                    .dwpsn file "../main.c",line 143,column 29,is_stmt,isa 2

           ADD       V9, SP, #8           ; [DPU_V7R4_PIPE0] |143|

           MOV       A3, #0               ; [DPU_V7R4_PIPE0] |143|

           MOV       A4, #1               ; [DPU_V7R4_PIPE1] |143|

           STMIA     V9, {A4,A3}           ; [DPU_V7R4_PIPE0] |143|

                    .dwpsn file "../main.c",line 145,column 5,is_stmt,isa 2

           ADD       V9, SP, #8           ; [DPU_V7R4_PIPE0] |145|

           LDMIA     SP, {V1,A4}           ; [DPU_V7R4_PIPE0] |145|

           LDMIA     V9, {V3,V2}           ; [DPU_V7R4_PIPE0] |145|

           ADDS     A3, V3, V1           ; [DPU_V7R4_PIPE0] |145|

           ADC       A2, V2, A4           ; [DPU_V7R4_PIPE0] |145|

           STMIA     SP, {A3,A2}           ; [DPU_V7R4_PIPE0] |145|

                    .dwpsn file "../main.c",line 147,column 5,is_stmt,isa 2

           LDMIA     SP, {A4,A3}           ; [DPU_V7R4_PIPE0] |147|

           MOV       V9, #0               ; [DPU_V7R4_PIPE0] |147|

           MOV       A2, #2               ; [DPU_V7R4_PIPE1] |147|

           ADDS     A2, A2, A4           ; [DPU_V7R4_PIPE0] |147|

           ADC       A1, V9, A3           ; [DPU_V7R4_PIPE0] |147|

           STMIA     SP, {A2,A1}           ; [DPU_V7R4_PIPE0] |147|

                    .dwpsn file "../main.c",line 148,column 1,is_stmt,isa 2

    What am I missing?

  • 0 in reply to PauloP
    TI__Guru**** 253380 points

    The problem is in the Dwarf debug information emitted by the compiler.  The Dwarf debug information has no effect on execution of the code.  It is used by a debugger, such as CCS, for such tasks such as associating an address with a line of code or a variable.  

    The problem occurs when a variable is assigned to a register pair.  The Dwarf debug information should specify both registers in the pair, but it only specifies one.  This does not occur in the specific case you tried, because no variables are assigned to registers.  

    CCS was changed to account for this lack of information in the debug information, so the effect of this bug is never seen by a user.  

    Thanks and regards,

    -George