Other Parts Discussed in Thread: C2000WARE
Tool/software: Code Composer Studio
Hi Guys, CCS9 won't download my code to my F28335 FLASH Memory. It WILL work if I download to RAM but I need it to download my code to FLASH and run from there.
I have changed the .CMD file to include FLASHA to FLASHH banks. When I BUILD my code CCS shows that its being stored in FLASHA as I have requested it to in the .cmd file.
My program builds fine with no errors. I then choose DEBUG and when using RAM it downloads to the F28335 fine but when using FLASH I get this error.
C28xx: Flash Programmer: Error encountered when writing to flash memory
C28xx: File Loader: Memory write failed: Unknown error
C28xx: GEL: File: /Users/a1234/Desktop/TI_Workspace/Max1010_MoveOS2_1/Debug/Max1010_MoveOS2_1.out: Load failed.
Below is my edited .CMD file. Can somebody please let me know what I have left out to download my code to FLASH and run from there.
Its very very URGENT.
Thanks and hope to hear from you soon.
Peter.
/*
// TI File $Revision: /main/11 $
// Checkin $Date: April 15, 2009 09:57:28 $
//###########################################################################
//
// FILE: 28335_RAM_lnk.cmd
//
// TITLE: Linker Command File For 28335 examples that run out of RAM
//
// This ONLY includes all SARAM blocks on the 28335 device.
// This does not include flash or OTP.
//
// Keep in mind that L0 and L1 are protected by the code
// security module.
//
// What this means is in most cases you will want to move to
// another memory map file which has more memory defined.
//
//###########################################################################
// $TI Release: $
// $Release Date: $
//###########################################################################
*/
/* ======================================================
// For Code Composer Studio V2.2 and later
// ---------------------------------------
// In addition to this memory linker command file,
// add the header linker command file directly to the project.
// The header linker command file is required to link the
// peripheral structures to the proper locations within
// the memory map.
//
// The header linker files are found in <base>\DSP2833x_Headers\cmd
//
// For BIOS applications add: DSP2833x_Headers_BIOS.cmd
// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd
========================================================= */
/* ======================================================
// For Code Composer Studio prior to V2.2
// --------------------------------------
// 1) Use one of the following -l statements to include the
// header linker command file in the project. The header linker
// file is required to link the peripheral structures to the proper
// locations within the memory map */
/* Uncomment this line to include file only for non-BIOS applications */
/* -l DSP2833x_Headers_nonBIOS.cmd */
/* Uncomment this line to include file only for BIOS applications */
/* -l DSP2833x_Headers_BIOS.cmd */
/* 2) In your project add the path to <base>\DSP2833x_headers\cmd to the
library search path under project->build options, linker tab,
library search path (-i).
/*========================================================= */
/* Define the memory block start/length for the F28335
PAGE 0 will be used to organize program sections
PAGE 1 will be used to organize data sections
Notes:
Memory blocks on F28335 are uniform (ie same
physical memory) in both PAGE 0 and PAGE 1.
That is the same memory region should not be
defined for both PAGE 0 and PAGE 1.
Doing so will result in corruption of program
and/or data.
L0/L1/L2 and L3 memory blocks are mirrored - that is
they can be accessed in high memory or low memory.
For simplicity only one instance is used in this
linker file.
Contiguous SARAM memory blocks can be combined
if required to create a larger memory block.
*/
MEMORY
{
PAGE 0 :
/* BEGIN is used for the "boot to SARAM" bootloader mode */
BEGIN : origin = 0x000000, length = 0x000002 /* Boot to M0 will go here */
RAMM0 : origin = 0x000050, length = 0x0003B0
RAML0 : origin = 0x008000, length = 0x001000
RAML1 : origin = 0x009000, length = 0x001000
RAML2 : origin = 0x00A000, length = 0x001000
RAML3 : origin = 0x00B000, length = 0x001000
ZONE7A : origin = 0x200000, length = 0x00FC00 /* XINTF zone 7 - program space */
CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
ADC_CAL : origin = 0x380080, length = 0x000009
RESET : origin = 0x3FFFC0, length = 0x000002
IQTABLES : origin = 0x3FE000, length = 0x000b50
IQTABLES2 : origin = 0x3FEB50, length = 0x00008c
FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0
BOOTROM : origin = 0x3FF27C, length = 0x000D44
FLASHA : origin = 0x338000, length = 0x007F80
FLASHB : origin = 0x330000, length = 0x007FFF
FLASHC : origin = 0x328000, length = 0x007FFF
FLASHD : origin = 0x320000, length = 0x007FFF
FLASHE : origin = 0x318000, length = 0x007FFF
FLASHF : origin = 0x310000, length = 0x007FFF
FLASHG : origin = 0x308000, length = 0x007FFF
FLASHH : origin = 0x300000, length = 0x007FFF
PAGE 1 :
/* BOOT_RSVD is used by the boot ROM for stack. */
/* This section is only reserved to keep the BOOT ROM from */
/* corrupting this area during the debug process */
BOOT_RSVD : origin = 0x000002, length = 0x00004E /* Part of M0, BOOT rom will use this for stack */
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
RAML4 : origin = 0x00C000, length = 0x001000
RAML5 : origin = 0x00D000, length = 0x001000
RAML6 : origin = 0x00E000, length = 0x001000
RAML7 : origin = 0x00F000, length = 0x001000
ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */
}
SECTIONS
{
/* Allocate program areas: */
.cinit : > FLASHA, PAGE = 0, ALIGN(4)
.pinit : > FLASHA, PAGE = 0, ALIGN(4)
.text : >> FLASHA | FLASHB | FLASHC | FLASHD | FLASHE | FLASHF | FLASHG | FLASHH PAGE = 0, ALIGN(4)
.switch : > FLASHA, PAGE = 0
codestart : > BEGIN, PAGE = 0, ALIGN(4)
/* Setup for "boot to SARAM" mode:
The codestart section (found in DSP28_CodeStartBranch.asm)
re-directs execution to the start of user code. */
/* codestart : > BEGIN, PAGE = 0 */
#ifdef __TI_COMPILER_VERSION__
#if __TI_COMPILER_VERSION__ >= 15009000
.TI.ramfunc : {} > RAML0, PAGE = 0
#else
ramfuncs : > RAML0, PAGE = 0
#endif
#endif
/*
.text : > RAML1, PAGE = 0
.cinit : > RAML0, PAGE = 0
.pinit : > RAML0, PAGE = 0
.switch : > RAML0, PAGE = 0
*/
.stack : > RAMM1, PAGE = 1
.ebss : > RAML4, PAGE = 1
.econst : > RAML5, PAGE = 1
.esysmem : > RAMM1, PAGE = 1
IQmath : > RAML1, PAGE = 0
IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD
/* Uncomment the section below if calling the IQNexp() or IQexp()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
{
IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
}
*/
FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD
DMARAML4 : > RAML4, PAGE = 1
DMARAML5 : > RAML5, PAGE = 1
DMARAML6 : > RAML6, PAGE = 1
DMARAML7 : > RAML7, PAGE = 1
ZONE7DATA : > ZONE7B, PAGE = 1
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used */
csm_rsvd : > CSM_RSVD PAGE = 0, TYPE = DSECT /* not used for SARAM examples */
csmpasswds : > CSM_PWL PAGE = 0, TYPE = DSECT /* not used for SARAM examples */
/* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */
.adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/
