ccsv4 local view problem

Stanley,

It really seems the Locals view is getting confused by the struct members KICK0R, KICK1R and HOST0CFG. I wonder if the compiler optimized these values somehow or if the view really has a bug. 

Would you do me a favor? Are you able to send a small test case or maybe tell which AM1808 example code reproduces this error? This way I could reproduce it here and see if I can either find a workaround or file a bug.

Thank you,

Rafael

Dear Rafael,

Thank you for your reply. i did some test and found the reason,but i dont understand why?

i get rid of the GEL file, the members of  the structure is viewed correctly.see the picture for the details. my code is as following .i attached mey GEL files(from am1808 experrimenter kit disk), please help me check if my GEL file is right? and where i can download the new and right  GEL files.

i have another question , you know , after the device power on, the KICK0R and KICK1R  register is 0 ,when i  executed the following code,  the value of the register is still o, it is right or not?

CSL_FINS(SysRegs->KICK0R, SYSCFG_KICK0R_KICK0, KICK0_KEY);
CSL_FINS(SysRegs->KICK1R, SYSCFG_KICK1R_KICK1, KICK1_KEY);

#define KICK0_KEY 0x83E70B13
#define KICK1_KEY 0x95A4F1E0
#define KICK_LOCK 0x00000000

U32 ConfigPll0(U32 clkmode, U32 pllm, U32 postdiv, U32 plldiv1, U32 plldiv2, U32 plldiv3, U32 plldiv7)
{
 U32 i;
 CSL_SyscfgRegsOvly SysRegs = (CSL_SyscfgRegsOvly) (CSL_SYSCFG_0_REGS);
 CSL_PllcRegsOvly Pllc = (CSL_PllcRegsOvly) (CSL_PLLC_0_REGS);
 
    // check the parameter invalidation
 if(clkmode > 1) return (ERR_INVALID_PARAMETER); 
 
 
    // unlock the system config registers.
 CSL_FINS(SysRegs->KICK0R, SYSCFG_KICK0R_KICK0, KICK0_KEY);
 CSL_FINS(SysRegs->KICK1R, SYSCFG_KICK1R_KICK1, KICK1_KEY);
 
    //unlock the pll config registers
 CSL_FINST(SysRegs->CFGCHIP0, SYSCFG_CFGCHIP0_PLL_MASTER_LOCK, FREE);
 
    //program the clock mode to oscilator crystal or square wave
 if(clkmode == 0)
 {
  CSL_FINST(Pllc->PLLCTL, PLLC_PLLCTL_CLKMODE, OSCIN);
 }
 else
 {
  CSL_FINST(Pllc->PLLCTL, PLLC_PLLCTL_CLKMODE, CLKIN );  
 }
 
   //clear the pllensrc to 0
 CSL_FINST(Pllc->PLLCTL, PLLC_PLLCTL_PLLENSRC, CLEAR);
 
 //select the oscin as the clock source in bypass mode
 CSL_FINST(Pllc->PLLCTL, PLLC_PLLCTL_EXTCLKSRC, DISABLE);
 
    // switch to bypass mode...wait 4 cycles to ensure it switches properly.
    CSL_FINST(Pllc->PLLCTL, PLLC_PLLCTL_PLLEN, BYPASS);
    for (i = 0; i < 4; i++) {}
   
     //reset pll
    CSL_FINST(Pllc->PLLCTL, PLLC_PLLCTL_PLLRST, ASSERT); 
   
    //power up
    CSL_FINST(Pllc->PLLCTL, PLLC_PLLCTL_PLLPWRDN,POWERED_UP); 
   
       /*Wait for PLL to reset properly. See PLL spec for PLL reset time - This step is not required here -step11*/
   for(i = 0; i < PLL_RESET_TIME_CNT; i++) {;}   /*128 MXI Cycles*/  
  
    // program the required multiplier value.
    CSL_FINS(Pllc->PLLM, PLLC_PLLM_PLLM,pllm);
   
       // program postdiv ratio.
   CSL_FINS(Pllc->POSTDIV, PLLC_POSTDIV_RATIO,postdiv);
   CSL_FINST(Pllc->POSTDIV, PLLC_POSTDIV_POSTDEN,ENABLE);

    // spin until all transitions are complete.
     while(CSL_FEXT(Pllc->PLLSTAT,PLLC_PLLSTAT_GOSTAT));
    
    // program the divisors.
 CSL_FINS(Pllc->PLLDIV1,PLLC_PLLDIV1_RATIO,plldiv1);
 CSL_FINST(Pllc->PLLDIV1,PLLC_PLLDIV1_D1EN,ENABLE);
 CSL_FINS(Pllc->PLLDIV2,PLLC_PLLDIV2_RATIO,plldiv2);
 CSL_FINST(Pllc->PLLDIV2,PLLC_PLLDIV2_D2EN,ENABLE);
 CSL_FINS(Pllc->PLLDIV3,PLLC_PLLDIV3_RATIO,plldiv3);
 CSL_FINST(Pllc->PLLDIV3,PLLC_PLLDIV3_D3EN,ENABLE);
 CSL_FINS(Pllc->PLLDIV4,PLLC_PLLDIV4_RATIO,(((plldiv1 + 1) * 4) - 1));
 CSL_FINST(Pllc->PLLDIV4,PLLC_PLLDIV4_D4EN,ENABLE);
 CSL_FINS(Pllc->PLLDIV6,PLLC_PLLDIV6_RATIO,plldiv1);
 CSL_FINST(Pllc->PLLDIV6,PLLC_PLLDIV6_D6EN,ENABLE);
 CSL_FINS(Pllc->PLLDIV7,PLLC_PLLDIV7_RATIO,plldiv7);
 CSL_FINST(Pllc->PLLDIV7,PLLC_PLLDIV7_D7EN,ENABLE); 
 
 //set the gostat to1
   CSL_FINST(Pllc->PLLSTAT, PLLC_PLLSTAT_GOSTAT,INPROG);
  
       // spin until all transitions are complete.
   while(CSL_FEXT(Pllc->PLLSTAT,PLLC_PLLSTAT_GOSTAT));
  
      /*Wait for PLL to reset properly. See PLL spec for PLL reset time - This step is not required here -step11*/
   for(i = 0; i < PLL_RESET_TIME_CNT; i++) {;}   /*128 MXI Cycles*/
  
   // bring pll out of reset and wait for pll to lock.
   CSL_FINST(Pllc->PLLCTL, PLLC_PLLCTL_PLLRST,DEASSERT);
  
   for (i = 0; i < PLL_LOCK_CYCLES; i++) {}
  
   CSL_FINST(Pllc->PLLCTL, PLLC_PLLCTL_PLLEN,PLL);
  
       //unlock the pll config registers
 CSL_FINST(SysRegs->CFGCHIP0, SYSCFG_CFGCHIP0_PLL_MASTER_LOCK, LOCK);
  
    // lock the system config registers.
 CSL_FINS(SysRegs->KICK0R, SYSCFG_KICK0R_KICK0, KICK_LOCK);
 CSL_FINS(SysRegs->KICK1R, SYSCFG_KICK1R_KICK1, KICK_LOCK);
 return (ERR_NO_ERROR);
}

7416.AM1808.rar

Stanley,

Thanks, I will take a look at the files as soon as possible and see what may be happening.

With regards to the KICK registers, unfortunately I am not very knowledgeable about the AM device. Can you send the second part of your question to the device forum? This way you will get better insights about the correct behaviour of these registers.

Thank you,

Rafael

Rafael,

Do you have any further information about the question to me?

thanks.