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MSP430 assembler/disassembler bug (symbolic addressing)

igorsk
Prodigy 20 points

I have to say that the current MSP430 manuals could really use some clarification in the instruction encodings area. It took me quite a while to figure out how the symbolic addressing works. Anyway, I think I found a bug in TI's assembler and disassembler for instructions with two symbolic (PC-relative) operands. The bug actually appears with the RLA pseudoinstruction. I have a short example.

input:

RLA.B 0x6BC(PC)
ADD.B 0x6BC(PC), 0x6BC(PC)
ADD.B 0x6BE(PC), 0x6BC(PC)
ADD.B 0x6BC(PC), 0x6BE(PC)

after assembing with asm430 and disassembling with dis430:

000008: D050 RLA.B 0x06c8
00000a: BC06
00000c: BC06
00000e: D050 RLA.B 0x06ce
000010: BC06
000012: BC06
000014: D050 ADD.B 0x06d4,0x06d4
000016: BE06
000018: BC06
00001a: D050 ADD.B 0x06d8,0x06dc
00001c: BC06
00001e: BE06

As you can see, both operands of the first two RLA.B/ADD.B were decoded to the same address, presumably because the PC value for the instruction was the same. However, the operands of the third instructuon are also decoded to the same value, despite different indexes. So which is right?

After spending some time in the debugger, I think the second one is right. It seems that the PC value for a PC-indexed operand is considered to be the address at which the index word resides. This is not spelled out in the manual though can be inferred by looking carefully at the example instruction. So this seems to be a bug in the assembler and disassembler. Here's how I think the bytes above should be disassembled:

0008: add.b 0x06C6, 0x06C8
000E: add.b 0x06CC, 0x06CE
0014: rla.b 0x06D4 / add.b 0x06d4,0x06d4
001A: add.b 0x06D8, 0x06DC

Interestingly, the symbolic references in the source are compiled correctly, presumably because the final index calculation is done by the linker and not assembler:

rla.w    W3
  |
  v
0xFC26: 5090 05DE 05DC   ADD.W W3,W3

Note how the index is adjusted with the PC change, but the disassembler did not collapse it to RLA.W.

P.S. Tested with asm430/dis430 3.3.0.0 (from CCS 4 4.1.3.00038).

P.P.S. The manuals describing MSP430X instructions should really have some explanation on how the ZC and repetition fields are reflected in the assembly. RPT prefix is mentioned in the example for RRAX but is not explained at all. ZC bit is totally mysterious, though I did figure out that it's used for RRUX.

  • TI__Guru**** 173310 points

    We will need to investigate this and get back to you.

  • in reply to AartiG
    TI__Prodigy 660 points

    I've written a bug report, SDSCM00039675, to capture this issue.  You can track the status here: SDOWP.  Enter the full id in the Find Record Id box.

    This form of addressing was unexpected in the RLA pseudo instruction.  Can you implement your code using another addressing mode?

    You have come to the correct conclusion about the PC value for a PC-indexed operand.  This makes the RLA pseudo instruction ambiguous when interpreted as an ADD if this addressing mode is used.

    Thanks,
    Steve

     

  • in reply to SteveR35416
    Prodigy 20 points

    Thanks for the confirmation! The code is not real life code, I was just debugging my disassembler and saw a difference :)

    I think you should encode RLA to have the same actual operands (i.e. with indexes differing by 2), and do the same check when simplifying the ADD instruction in the disassembler.