CCS4 load problem with C6745

Ron,

I don't recall seeing such inversion on the instruction words before. The loader indeed seems to be inverting the two words. Does this code run in a evaluation board - the C6747DSK, for example? 

Are you bootloading the board or simply loading the code via the emulator? If loading via the emulator and since this memory address is internal, it rules out any memory routing issues. Maybe something related to the boot configuration of your device (check this post for some comments on boot modes).

I still need to get back and think about other things, but the emulator seems to be loading the data consistently (i.e., the JTAG communications seem to have no issues) since it did not throw any data verification failed errors.  

In the meantime, if you could send your .out file, the linker map file and the assembly listing file that would help.

Thank you,

Rafael

******************************************************************************
               TMS320C6x Linker PC v7.0.3                     
******************************************************************************
>> Linked Thu Mar 17 15:38:40 2011

OUTPUT FILE NAME:   <CT-610DSP.out>
ENTRY POINT SYMBOL: "_c_int00"  address: 00800a60

MEMORY CONFIGURATION

         name            origin    length      used     unused   attr    fill
----------------------  --------  ---------  --------  --------  ----  --------
  DSP_L2_RAM_txt        00800000   00030000  00000ce8  0002f318  RWIX
  DSP_L2_RAM_data       00830000   00010000  00000000  00010000  RWIX
  DSP_L1P_RAM           00e00000   00007000  00000000  00007000  RWIX
  DSP_L1D_RAM           00f00000   00007000  00000000  00007000  RWIX

SECTION ALLOCATION MAP

 output                                  attributes/
section   page    origin      length       input sections
--------  ----  ----------  ----------   ----------------
.bss       0    00800000    00000000     UNINITIALIZED

.stack     0    00800000    00000800     UNINITIALIZED
                  00800000    00000008     rts6740.lib : boot.obj (.stack)
                  00800008    000007f8     --HOLE--

.data      0    00800000    00000000     UNINITIALIZED

.text      0    00800800    00000380    
                  00800800    000000e0     rts6740.lib : autoinit.obj (.text:__auto_init)
                  008008e0    000000e0                 : exit.obj (.text:_exit)
                  008009c0    000000a0                 : memcpy64.obj (.text:_memcpy)
                  00800a60    00000080                 : boot.obj (.text:_c_int00)
                  00800ae0    00000040                 : args_main.obj (.text:__args_main)
                  00800b20    00000020     CT610dspMain.obj (.text)
                  00800b40    00000020     rts6740.lib : _lock.obj (.text:__nop)
                  00800b60    00000020                 : exit.obj (.text:_abort)

.vecs      0    00800b80    00000100    
                  00800b80    00000100     CT-610dspAsm.obj (.vecs)

.cinit     0    00800c80    00000054    
                  00800c80    0000002c     rts6740.lib : exit.obj (.cinit)
                  00800cac    00000004     --HOLE-- [fill = 0]
                  00800cb0    0000001c                 : _lock.obj (.cinit)
                  00800ccc    00000004     --HOLE-- [fill = 0]
                  00800cd0    00000004     (.pad.cinit) [fill = 0]

.far       0    00800cd4    00000014     UNINITIALIZED
                  00800cd4    0000000c     rts6740.lib : exit.obj (.far)
                  00800ce0    00000008                 : _lock.obj (.far)

GLOBAL SYMBOLS: SORTED ALPHABETICALLY BY Name

address    name
--------   ----
00800000   $bss
00800000   .bss
00800000   .data
00800800   .text
00800b60   C$$EXIT
00800800   __STACK_END
00000800   __STACK_SIZE
00000001   __TI_args_main
00800cdc   ___TI_enable_exit_profile_output
ffffffff   ___TI_pprof_out_hndl
ffffffff   ___TI_prof_data_size
ffffffff   ___TI_prof_data_start
ffffffff   ___binit__
00800000   ___bss__
ffffffff   ___c_args__
00800c80   ___cinit__
00800000   ___data__
00800000   ___edata__
00800000   ___end__
00800b80   ___etext__
ffffffff   ___pinit__
00800800   ___text__
00800ae0   __args_main
00800800   __auto_init
00800cd4   __cleanup_ptr
00800cd8   __dtors_ptr
00800ce0   __lock
00800b40   __nop
00800000   __stack
00800ce4   __unlock
00800b60   _abort
00800a60   _c_int00
008008e0   _exit
00800b20   _main
008009c0   _memcpy
ffffffff   binit
00800c80   cinit
00800000   edata
00800000   end
00800b80   etext
ffffffff   pinit

GLOBAL SYMBOLS: SORTED BY Symbol Address

address    name
--------   ----
00000001   __TI_args_main
00000800   __STACK_SIZE
00800000   $bss
00800000   .bss
00800000   .data
00800000   ___bss__
00800000   ___data__
00800000   ___edata__
00800000   ___end__
00800000   __stack
00800000   edata
00800000   end
00800800   .text
00800800   __STACK_END
00800800   ___text__
00800800   __auto_init
008008e0   _exit
008009c0   _memcpy
00800a60   _c_int00
00800ae0   __args_main
00800b20   _main
00800b40   __nop
00800b60   C$$EXIT
00800b60   _abort
00800b80   ___etext__
00800b80   etext
00800c80   ___cinit__
00800c80   cinit
00800cd4   __cleanup_ptr
00800cd8   __dtors_ptr
00800cdc   ___TI_enable_exit_profile_output
00800ce0   __lock
00800ce4   __unlock
ffffffff   ___TI_pprof_out_hndl
ffffffff   ___TI_prof_data_size
ffffffff   ___TI_prof_data_start
ffffffff   ___binit__
ffffffff   ___c_args__
ffffffff   ___pinit__
ffffffff   binit
ffffffff   pinit

[41 symbols]

TMS320C6x Assembler PC v7.0.3 Thu Mar 17 15:38:40 2011

Tools Copyright (c) 1996-2010 Texas Instruments Incorporated
CT610dspMain.asm                                                     PAGE    1

       1                    ;******************************************************************************
       2                    ;* TMS320C6x C/C++ Codegen                                          PC v7.0.3 *
       3                    ;* Date/Time created: Thu Mar 17 15:38:40 2011                                *
       4                    ;******************************************************************************
       5                            .compiler_opts --abi=coffabi --c64p_l1d_workaround=off --endian=little --hll_source=on --long_
       6                   
       7                    ;******************************************************************************
       8                    ;* GLOBAL FILE PARAMETERS                                                     *
       9                    ;*                                                                            *
      10                    ;*   Architecture      : TMS320C674x                                          *
      11                    ;*   Optimization      : Disabled                                             *
      12                    ;*   Optimizing for    : Compile time, Ease of Development                    *
      13                    ;*                       Based on options: no -o, no -ms                      *
      14                    ;*   Endian            : Little                                               *
      15                    ;*   Interrupt Thrshld : Disabled                                             *
      16                    ;*   Data Access Model : Far Aggregate Data                                   *
      17                    ;*   Pipelining        : Disabled                                             *
      18                    ;*   Memory Aliases    : Presume are aliases (pessimistic)                    *
      19                    ;*   Debug Info        : DWARF Debug                                          *
      20                    ;*                                                                            *
      21                    ;******************************************************************************
      22                   
      23                            .asg    A15, FP
      24                            .asg    B14, DP
      25                            .asg    B15, SP
      26                            .global $bss
      27                   
      28                   
      29                    $C$DW$CU        .dwtag  DW_TAG_compile_unit
      30                            .dwattr $C$DW$CU, DW_AT_name("../CT610dspMain.c")
      31                            .dwattr $C$DW$CU, DW_AT_producer("TMS320C6x C/C++ Codegen PC v7.0.3 Copyright (c) 1996-2010 Te
      32                            .dwattr $C$DW$CU, DW_AT_TI_version(0x01)
      33                            .dwattr $C$DW$CU, DW_AT_comp_dir("C:\ENG\Projects\Controller Software\CT-610 DSP\CT-610 DSP\De
      34                    ;       C:\Program Files\Texas Instruments\ccsv4.2\ccsv4\tools\compiler\c6000\bin\acp6x.exe -@C:\\DOCU
      35 00000000                   .sect   ".text"
      36                            .clink
      37                            .global _main
      38                   
      39                    $C$DW$1 .dwtag  DW_TAG_subprogram, DW_AT_name("main")
      40                            .dwattr $C$DW$1, DW_AT_low_pc(_main)
      41                            .dwattr $C$DW$1, DW_AT_high_pc(0x00)
      42                            .dwattr $C$DW$1, DW_AT_TI_symbol_name("_main")
      43                            .dwattr $C$DW$1, DW_AT_external
      44                            .dwattr $C$DW$1, DW_AT_TI_begin_file("../CT610dspMain.c")
      45                            .dwattr $C$DW$1, DW_AT_TI_begin_line(0x6f)
      46                            .dwattr $C$DW$1, DW_AT_TI_begin_column(0x06)
      47                            .dwattr $C$DW$1, DW_AT_TI_max_frame_size(0x00)
      48                            .dwpsn  file "../CT610dspMain.c",line 111,column 17,is_stmt,address _main
      49                   
      50                            .dwfde $C$DW$CIE, _main
      51                   
      52                    ;******************************************************************************
      53                    ;* FUNCTION NAME: main                                                        *
      54                    ;*                                                                            *
      55                    ;*   Regs Modified     :                                                      *
TMS320C6x Assembler PC v7.0.3 Thu Mar 17 15:38:40 2011

Tools Copyright (c) 1996-2010 Texas Instruments Incorporated
CT610dspMain.asm                                                     PAGE    2

      56                    ;*   Regs Used         : B3                                                   *
      57                    ;*   Local Frame Size  : 0 Args + 0 Auto + 0 Save = 0 byte                    *
      58                    ;******************************************************************************
      59 00000000           _main:
      60                    ;** --------------------------------------------------------------------------*
      61                            .dwcfi  cfa_offset, 0
      62                            .dwcfi  save_reg_to_reg, 228, 19
      63                            .dwpsn  file "../CT610dspMain.c",line 112,column 9,is_stmt
      64                    ;*----------------------------------------------------------------------------*
      65                    ;*   SOFTWARE PIPELINE INFORMATION
      66                    ;*      Disqualified loop: Software pipelining disabled
      67                    ;*----------------------------------------------------------------------------*
      68 00000000           $C$L1:   
      69 00000000           $C$DW$L$_main$2$B:
      70                            .dwpsn  file "../CT610dspMain.c",line 113,column 3,is_stmt
      71 00000000 00010000          nop 10
 "CT610dspMain.asm", WARNING! at line 71: [W0000] Delay slot count must be 1 to 9, reducing to 9
      72                            .dwpsn  file "../CT610dspMain.c",line 112,column 9,is_stmt
      73 00000004 00000010             B       .S1     $C$L1             ; |112|
      74 00000008 00008000             NOP             5
      75                               ; BRANCH OCCURS {$C$L1}           ; |112|
      76 0000000c           $C$DW$L$_main$2$E:
      77                    ;** --------------------------------------------------------------------------*
      78                            .dwcfi  cfa_offset, 0
      79                   
      80                    $C$DW$2 .dwtag  DW_TAG_TI_loop
      81                            .dwattr $C$DW$2, DW_AT_name("C:\ENG\Projects\Controller Software\CT-610 DSP\CT-610 DSP\Debug\C
      82                            .dwattr $C$DW$2, DW_AT_TI_begin_file("../CT610dspMain.c")
      83                            .dwattr $C$DW$2, DW_AT_TI_begin_line(0x70)
      84                            .dwattr $C$DW$2, DW_AT_TI_end_line(0x72)
      85                    $C$DW$3 .dwtag  DW_TAG_TI_loop_range
      86                            .dwattr $C$DW$3, DW_AT_low_pc($C$DW$L$_main$2$B)
      87                            .dwattr $C$DW$3, DW_AT_high_pc($C$DW$L$_main$2$E)
      88                            .dwendtag $C$DW$2
      89                   
      90                            .dwattr $C$DW$1, DW_AT_TI_end_file("../CT610dspMain.c")
      91                            .dwattr $C$DW$1, DW_AT_TI_end_line(0x73)
      92                            .dwattr $C$DW$1, DW_AT_TI_end_column(0x01)
      93                            .dwendentry
      94                            .dwendtag $C$DW$1
      95                   
      96                   
      97                    ;******************************************************************************
      98                    ;* TYPE INFORMATION                                                           *
      99                    ;******************************************************************************
     100                    $C$DW$T$4       .dwtag  DW_TAG_base_type
     101                            .dwattr $C$DW$T$4, DW_AT_encoding(DW_ATE_boolean)
     102                            .dwattr $C$DW$T$4, DW_AT_name("bool")
     103                            .dwattr $C$DW$T$4, DW_AT_byte_size(0x01)
     104                    $C$DW$T$5       .dwtag  DW_TAG_base_type
     105                            .dwattr $C$DW$T$5, DW_AT_encoding(DW_ATE_signed_char)
     106                            .dwattr $C$DW$T$5, DW_AT_name("signed char")
     107                            .dwattr $C$DW$T$5, DW_AT_byte_size(0x01)
     108                    $C$DW$T$6       .dwtag  DW_TAG_base_type
     109                            .dwattr $C$DW$T$6, DW_AT_encoding(DW_ATE_unsigned_char)
TMS320C6x Assembler PC v7.0.3 Thu Mar 17 15:38:40 2011

Tools Copyright (c) 1996-2010 Texas Instruments Incorporated
CT610dspMain.asm                                                     PAGE    3

     110                            .dwattr $C$DW$T$6, DW_AT_name("unsigned char")
     111                            .dwattr $C$DW$T$6, DW_AT_byte_size(0x01)
     112                    $C$DW$T$7       .dwtag  DW_TAG_base_type
     113                            .dwattr $C$DW$T$7, DW_AT_encoding(DW_ATE_signed_char)
     114                            .dwattr $C$DW$T$7, DW_AT_name("wchar_t")
     115                            .dwattr $C$DW$T$7, DW_AT_byte_size(0x02)
     116                    $C$DW$T$8       .dwtag  DW_TAG_base_type
     117                            .dwattr $C$DW$T$8, DW_AT_encoding(DW_ATE_signed)
     118                            .dwattr $C$DW$T$8, DW_AT_name("short")
     119                            .dwattr $C$DW$T$8, DW_AT_byte_size(0x02)
     120                    $C$DW$T$9       .dwtag  DW_TAG_base_type
     121                            .dwattr $C$DW$T$9, DW_AT_encoding(DW_ATE_unsigned)
     122                            .dwattr $C$DW$T$9, DW_AT_name("unsigned short")
     123                            .dwattr $C$DW$T$9, DW_AT_byte_size(0x02)
     124                    $C$DW$T$10      .dwtag  DW_TAG_base_type
     125                            .dwattr $C$DW$T$10, DW_AT_encoding(DW_ATE_signed)
     126                            .dwattr $C$DW$T$10, DW_AT_name("int")
     127                            .dwattr $C$DW$T$10, DW_AT_byte_size(0x04)
     128                    $C$DW$T$11      .dwtag  DW_TAG_base_type
     129                            .dwattr $C$DW$T$11, DW_AT_encoding(DW_ATE_unsigned)
     130                            .dwattr $C$DW$T$11, DW_AT_name("unsigned int")
     131                            .dwattr $C$DW$T$11, DW_AT_byte_size(0x04)
     132                    $C$DW$T$12      .dwtag  DW_TAG_base_type
     133                            .dwattr $C$DW$T$12, DW_AT_encoding(DW_ATE_signed)
     134                            .dwattr $C$DW$T$12, DW_AT_name("long")
     135                            .dwattr $C$DW$T$12, DW_AT_byte_size(0x08)
     136                            .dwattr $C$DW$T$12, DW_AT_bit_size(0x28)
     137                            .dwattr $C$DW$T$12, DW_AT_bit_offset(0x18)
     138                    $C$DW$T$13      .dwtag  DW_TAG_base_type
     139                            .dwattr $C$DW$T$13, DW_AT_encoding(DW_ATE_unsigned)
     140                            .dwattr $C$DW$T$13, DW_AT_name("unsigned long")
     141                            .dwattr $C$DW$T$13, DW_AT_byte_size(0x08)
     142                            .dwattr $C$DW$T$13, DW_AT_bit_size(0x28)
     143                            .dwattr $C$DW$T$13, DW_AT_bit_offset(0x18)
     144                    $C$DW$T$14      .dwtag  DW_TAG_base_type
     145                            .dwattr $C$DW$T$14, DW_AT_encoding(DW_ATE_signed)
     146                            .dwattr $C$DW$T$14, DW_AT_name("long long")
     147                            .dwattr $C$DW$T$14, DW_AT_byte_size(0x08)
     148                    $C$DW$T$15      .dwtag  DW_TAG_base_type
     149                            .dwattr $C$DW$T$15, DW_AT_encoding(DW_ATE_unsigned)
     150                            .dwattr $C$DW$T$15, DW_AT_name("unsigned long long")
     151                            .dwattr $C$DW$T$15, DW_AT_byte_size(0x08)
     152                    $C$DW$T$16      .dwtag  DW_TAG_base_type
     153                            .dwattr $C$DW$T$16, DW_AT_encoding(DW_ATE_float)
     154                            .dwattr $C$DW$T$16, DW_AT_name("float")
     155                            .dwattr $C$DW$T$16, DW_AT_byte_size(0x04)
     156                    $C$DW$T$17      .dwtag  DW_TAG_base_type
     157                            .dwattr $C$DW$T$17, DW_AT_encoding(DW_ATE_float)
     158                            .dwattr $C$DW$T$17, DW_AT_name("double")
     159                            .dwattr $C$DW$T$17, DW_AT_byte_size(0x08)
     160                    $C$DW$T$18      .dwtag  DW_TAG_base_type
     161                            .dwattr $C$DW$T$18, DW_AT_encoding(DW_ATE_float)
     162                            .dwattr $C$DW$T$18, DW_AT_name("long double")
     163                            .dwattr $C$DW$T$18, DW_AT_byte_size(0x08)
     164                            .dwattr $C$DW$CU, DW_AT_language(DW_LANG_C)
TMS320C6x Assembler PC v7.0.3 Thu Mar 17 15:38:40 2011

Tools Copyright (c) 1996-2010 Texas Instruments Incorporated
CT610dspMain.asm                                                     PAGE    4

     165                   
     166                    ;***************************************************************
     167                    ;* DWARF CIE ENTRIES                                           *
     168                    ;***************************************************************
     169                   
     170                    $C$DW$CIE       .dwcie 228
     171                            .dwcfi  cfa_register, 31
     172                            .dwcfi  cfa_offset, 0
     173                            .dwcfi  undefined, 0
     174                            .dwcfi  undefined, 1
     175                            .dwcfi  undefined, 2
     176                            .dwcfi  undefined, 3
     177                            .dwcfi  undefined, 4
     178                            .dwcfi  undefined, 5
     179                            .dwcfi  undefined, 6
     180                            .dwcfi  undefined, 7
     181                            .dwcfi  undefined, 8
     182                            .dwcfi  undefined, 9
     183                            .dwcfi  same_value, 10
     184                            .dwcfi  same_value, 11
     185                            .dwcfi  same_value, 12
     186                            .dwcfi  same_value, 13
     187                            .dwcfi  same_value, 14
     188                            .dwcfi  same_value, 15
     189                            .dwcfi  undefined, 16
     190                            .dwcfi  undefined, 17
     191                            .dwcfi  undefined, 18
     192                            .dwcfi  undefined, 19
     193                            .dwcfi  undefined, 20
     194                            .dwcfi  undefined, 21
     195                            .dwcfi  undefined, 22
     196                            .dwcfi  undefined, 23
     197                            .dwcfi  undefined, 24
     198                            .dwcfi  undefined, 25
     199                            .dwcfi  same_value, 26
     200                            .dwcfi  same_value, 27
     201                            .dwcfi  same_value, 28
     202                            .dwcfi  same_value, 29
     203                            .dwcfi  same_value, 30
     204                            .dwcfi  same_value, 31
     205                            .dwcfi  same_value, 32
     206                            .dwcfi  undefined, 33
     207                            .dwcfi  undefined, 34
     208                            .dwcfi  undefined, 35
     209                            .dwcfi  undefined, 36
     210                            .dwcfi  undefined, 37
     211                            .dwcfi  undefined, 38
     212                            .dwcfi  undefined, 39
     213                            .dwcfi  undefined, 40
     214                            .dwcfi  undefined, 41
     215                            .dwcfi  undefined, 42
     216                            .dwcfi  undefined, 43
     217                            .dwcfi  undefined, 44
     218                            .dwcfi  undefined, 45
     219                            .dwcfi  undefined, 46
TMS320C6x Assembler PC v7.0.3 Thu Mar 17 15:38:40 2011

Tools Copyright (c) 1996-2010 Texas Instruments Incorporated
CT610dspMain.asm                                                     PAGE    5

     220                            .dwcfi  undefined, 47
     221                            .dwcfi  undefined, 48
     222                            .dwcfi  undefined, 49
     223                            .dwcfi  undefined, 50
     224                            .dwcfi  undefined, 51
     225                            .dwcfi  undefined, 52
     226                            .dwcfi  undefined, 53
     227                            .dwcfi  undefined, 54
     228                            .dwcfi  undefined, 55
     229                            .dwcfi  undefined, 56
     230                            .dwcfi  undefined, 57
     231                            .dwcfi  undefined, 58
     232                            .dwcfi  undefined, 59
     233                            .dwcfi  undefined, 60
     234                            .dwcfi  undefined, 61
     235                            .dwcfi  undefined, 62
     236                            .dwcfi  undefined, 63
     237                            .dwcfi  undefined, 64
     238                            .dwcfi  undefined, 65
     239                            .dwcfi  undefined, 66
     240                            .dwcfi  undefined, 67
     241                            .dwcfi  undefined, 68
     242                            .dwcfi  undefined, 69
     243                            .dwcfi  undefined, 70
     244                            .dwcfi  undefined, 71
     245                            .dwcfi  undefined, 72
     246                            .dwcfi  undefined, 73
     247                            .dwcfi  undefined, 74
     248                            .dwcfi  undefined, 75
     249                            .dwcfi  undefined, 76
     250                            .dwcfi  undefined, 77
     251                            .dwcfi  undefined, 78
     252                            .dwcfi  undefined, 79
     253                            .dwcfi  undefined, 80
     254                            .dwcfi  undefined, 81
     255                            .dwcfi  undefined, 82
     256                            .dwcfi  undefined, 83
     257                            .dwcfi  undefined, 84
     258                            .dwcfi  undefined, 85
     259                            .dwcfi  undefined, 86
     260                            .dwcfi  undefined, 87
     261                            .dwcfi  undefined, 88
     262                            .dwcfi  undefined, 89
     263                            .dwcfi  undefined, 90
     264                            .dwcfi  undefined, 91
     265                            .dwcfi  undefined, 92
     266                            .dwcfi  undefined, 93
     267                            .dwcfi  undefined, 94
     268                            .dwcfi  undefined, 95
     269                            .dwcfi  undefined, 96
     270                            .dwcfi  undefined, 97
     271                            .dwcfi  undefined, 98
     272                            .dwcfi  undefined, 99
     273                            .dwcfi  undefined, 100
     274                            .dwcfi  undefined, 101
TMS320C6x Assembler PC v7.0.3 Thu Mar 17 15:38:40 2011

Tools Copyright (c) 1996-2010 Texas Instruments Incorporated
CT610dspMain.asm                                                     PAGE    6

     275                            .dwcfi  undefined, 102
     276                            .dwcfi  undefined, 103
     277                            .dwcfi  undefined, 104
     278                            .dwcfi  undefined, 105
     279                            .dwcfi  undefined, 106
     280                            .dwcfi  undefined, 107
     281                            .dwcfi  undefined, 108
     282                            .dwcfi  undefined, 109
     283                            .dwcfi  undefined, 110
     284                            .dwcfi  undefined, 111
     285                            .dwcfi  undefined, 112
     286                            .dwcfi  undefined, 113
     287                            .dwcfi  undefined, 114
     288                            .dwcfi  undefined, 115
     289                            .dwcfi  undefined, 116
     290                            .dwcfi  undefined, 117
     291                            .dwcfi  undefined, 118
     292                            .dwcfi  undefined, 119
     293                            .dwcfi  undefined, 120
     294                            .dwcfi  undefined, 121
     295                            .dwcfi  undefined, 122
     296                            .dwcfi  undefined, 123
     297                            .dwcfi  undefined, 124
     298                            .dwcfi  undefined, 125
     299                            .dwcfi  undefined, 126
     300                            .dwcfi  undefined, 127
     301                            .dwcfi  undefined, 128
     302                            .dwcfi  undefined, 129
     303                            .dwcfi  undefined, 130
     304                            .dwcfi  undefined, 131
     305                            .dwcfi  undefined, 132
     306                            .dwcfi  undefined, 133
     307                            .dwcfi  undefined, 134
     308                            .dwcfi  undefined, 135
     309                            .dwcfi  undefined, 136
     310                            .dwcfi  undefined, 137
     311                            .dwcfi  undefined, 138
     312                            .dwcfi  undefined, 139
     313                            .dwcfi  undefined, 140
     314                            .dwcfi  undefined, 141
     315                            .dwcfi  undefined, 142
     316                            .dwcfi  undefined, 143
     317                            .dwcfi  undefined, 144
     318                            .dwcfi  undefined, 145
     319                            .dwcfi  undefined, 146
     320                            .dwcfi  undefined, 147
     321                            .dwcfi  undefined, 148
     322                            .dwcfi  undefined, 149
     323                            .dwcfi  undefined, 150
     324                            .dwcfi  undefined, 151
     325                            .dwcfi  undefined, 152
     326                            .dwcfi  undefined, 153
     327                            .dwcfi  undefined, 154
     328                            .dwcfi  undefined, 155
     329                            .dwcfi  undefined, 156
TMS320C6x Assembler PC v7.0.3 Thu Mar 17 15:38:40 2011

Tools Copyright (c) 1996-2010 Texas Instruments Incorporated
CT610dspMain.asm                                                     PAGE    7

     330                            .dwcfi  undefined, 157
     331                            .dwcfi  undefined, 158
     332                            .dwcfi  undefined, 159
     333                            .dwcfi  undefined, 160
     334                            .dwcfi  undefined, 161
     335                            .dwcfi  undefined, 162
     336                            .dwcfi  undefined, 163
     337                            .dwcfi  undefined, 164
     338                            .dwcfi  undefined, 165
     339                            .dwcfi  undefined, 166
     340                            .dwcfi  undefined, 167
     341                            .dwcfi  undefined, 168
     342                            .dwcfi  undefined, 169
     343                            .dwcfi  undefined, 170
     344                            .dwcfi  undefined, 171
     345                            .dwcfi  undefined, 172
     346                            .dwcfi  undefined, 173
     347                            .dwcfi  undefined, 174
     348                            .dwcfi  undefined, 175
     349                            .dwcfi  undefined, 176
     350                            .dwcfi  undefined, 177
     351                            .dwcfi  undefined, 178
     352                            .dwcfi  undefined, 179
     353                            .dwcfi  undefined, 180
     354                            .dwcfi  undefined, 181
     355                            .dwcfi  undefined, 182
     356                            .dwcfi  undefined, 183
     357                            .dwcfi  undefined, 184
     358                            .dwcfi  undefined, 185
     359                            .dwcfi  undefined, 186
     360                            .dwcfi  undefined, 187
     361                            .dwcfi  undefined, 188
     362                            .dwcfi  undefined, 189
     363                            .dwcfi  undefined, 190
     364                            .dwcfi  undefined, 191
     365                            .dwcfi  undefined, 192
     366                            .dwcfi  undefined, 193
     367                            .dwcfi  undefined, 194
     368                            .dwcfi  undefined, 195
     369                            .dwcfi  undefined, 196
     370                            .dwcfi  undefined, 197
     371                            .dwcfi  undefined, 198
     372                            .dwcfi  undefined, 199
     373                            .dwcfi  undefined, 200
     374                            .dwcfi  undefined, 201
     375                            .dwcfi  undefined, 202
     376                            .dwcfi  undefined, 203
     377                            .dwcfi  undefined, 204
     378                            .dwcfi  undefined, 205
     379                            .dwcfi  undefined, 206
     380                            .dwcfi  undefined, 207
     381                            .dwcfi  undefined, 208
     382                            .dwcfi  undefined, 209
     383                            .dwcfi  undefined, 210
     384                            .dwcfi  undefined, 211
TMS320C6x Assembler PC v7.0.3 Thu Mar 17 15:38:40 2011

Tools Copyright (c) 1996-2010 Texas Instruments Incorporated
CT610dspMain.asm                                                     PAGE    8

     385                            .dwcfi  undefined, 212
     386                            .dwcfi  undefined, 213
     387                            .dwcfi  undefined, 214
     388                            .dwcfi  undefined, 215
     389                            .dwcfi  undefined, 216
     390                            .dwcfi  undefined, 217
     391                            .dwcfi  undefined, 218
     392                            .dwcfi  undefined, 219
     393                            .dwcfi  undefined, 220
     394                            .dwcfi  undefined, 221
     395                            .dwcfi  undefined, 222
     396                            .dwcfi  undefined, 223
     397                            .dwcfi  undefined, 224
     398                            .dwcfi  undefined, 225
     399                            .dwcfi  undefined, 226
     400                            .dwcfi  undefined, 227
     401                            .dwcfi  undefined, 228
     402                            .dwendentry
     403                   
     404                    ;***************************************************************
     405                    ;* DWARF REGISTER MAP                                          *
     406                    ;***************************************************************
     407                   
     408                    $C$DW$4 .dwtag  DW_TAG_TI_assign_register, DW_AT_name("A0")
     409                            .dwattr $C$DW$4, DW_AT_location[DW_OP_reg0]
     410                    $C$DW$5 .dwtag  DW_TAG_TI_assign_register, DW_AT_name("A1")
     411                            .dwattr $C$DW$5, DW_AT_location[DW_OP_reg1]
     412                    $C$DW$6 .dwtag  DW_TAG_TI_assign_register, DW_AT_name("A2")
     413                            .dwattr $C$DW$6, DW_AT_location[DW_OP_reg2]
     414                    $C$DW$7 .dwtag  DW_TAG_TI_assign_register, DW_AT_name("A3")
     415                            .dwattr $C$DW$7, DW_AT_location[DW_OP_reg3]
     416                    $C$DW$8 .dwtag  DW_TAG_TI_assign_register, DW_AT_name("A4")
     417                            .dwattr $C$DW$8, DW_AT_location[DW_OP_reg4]
     418                    $C$DW$9 .dwtag  DW_TAG_TI_assign_register, DW_AT_name("A5")
     419                            .dwattr $C$DW$9, DW_AT_location[DW_OP_reg5]
     420                    $C$DW$10        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("A6")
     421                            .dwattr $C$DW$10, DW_AT_location[DW_OP_reg6]
     422                    $C$DW$11        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("A7")
     423                            .dwattr $C$DW$11, DW_AT_location[DW_OP_reg7]
     424                    $C$DW$12        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("A8")
     425                            .dwattr $C$DW$12, DW_AT_location[DW_OP_reg8]
     426                    $C$DW$13        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("A9")
     427                            .dwattr $C$DW$13, DW_AT_location[DW_OP_reg9]
     428                    $C$DW$14        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("A10")
     429                            .dwattr $C$DW$14, DW_AT_location[DW_OP_reg10]
     430                    $C$DW$15        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("A11")
     431                            .dwattr $C$DW$15, DW_AT_location[DW_OP_reg11]
     432                    $C$DW$16        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("A12")
     433                            .dwattr $C$DW$16, DW_AT_location[DW_OP_reg12]
     434                    $C$DW$17        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("A13")
     435                            .dwattr $C$DW$17, DW_AT_location[DW_OP_reg13]
     436                    $C$DW$18        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("A14")
     437                            .dwattr $C$DW$18, DW_AT_location[DW_OP_reg14]
     438                    $C$DW$19        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("A15")
     439                            .dwattr $C$DW$19, DW_AT_location[DW_OP_reg15]
TMS320C6x Assembler PC v7.0.3 Thu Mar 17 15:38:40 2011

Tools Copyright (c) 1996-2010 Texas Instruments Incorporated
CT610dspMain.asm                                                     PAGE    9

     440                    $C$DW$20        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("B0")
     441                            .dwattr $C$DW$20, DW_AT_location[DW_OP_reg16]
     442                    $C$DW$21        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("B1")
     443                            .dwattr $C$DW$21, DW_AT_location[DW_OP_reg17]
     444                    $C$DW$22        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("B2")
     445                            .dwattr $C$DW$22, DW_AT_location[DW_OP_reg18]
     446                    $C$DW$23        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("B3")
     447                            .dwattr $C$DW$23, DW_AT_location[DW_OP_reg19]
     448                    $C$DW$24        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("B4")
     449                            .dwattr $C$DW$24, DW_AT_location[DW_OP_reg20]
     450                    $C$DW$25        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("B5")
     451                            .dwattr $C$DW$25, DW_AT_location[DW_OP_reg21]
     452                    $C$DW$26        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("B6")
     453                            .dwattr $C$DW$26, DW_AT_location[DW_OP_reg22]
     454                    $C$DW$27        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("B7")
     455                            .dwattr $C$DW$27, DW_AT_location[DW_OP_reg23]
     456                    $C$DW$28        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("B8")
     457                            .dwattr $C$DW$28, DW_AT_location[DW_OP_reg24]
     458                    $C$DW$29        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("B9")
     459                            .dwattr $C$DW$29, DW_AT_location[DW_OP_reg25]
     460                    $C$DW$30        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("B10")
     461                            .dwattr $C$DW$30, DW_AT_location[DW_OP_reg26]
     462                    $C$DW$31        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("B11")
     463                            .dwattr $C$DW$31, DW_AT_location[DW_OP_reg27]
     464                    $C$DW$32        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("B12")
     465                            .dwattr $C$DW$32, DW_AT_location[DW_OP_reg28]
     466                    $C$DW$33        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("B13")
     467                            .dwattr $C$DW$33, DW_AT_location[DW_OP_reg29]
     468                    $C$DW$34        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("DP")
     469                            .dwattr $C$DW$34, DW_AT_location[DW_OP_reg30]
     470                    $C$DW$35        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("SP")
     471                            .dwattr $C$DW$35, DW_AT_location[DW_OP_reg31]
     472                    $C$DW$36        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("FP")
     473                            .dwattr $C$DW$36, DW_AT_location[DW_OP_regx 0x20]
     474                    $C$DW$37        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("PC")
     475                            .dwattr $C$DW$37, DW_AT_location[DW_OP_regx 0x21]
     476                    $C$DW$38        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("IRP")
     477                            .dwattr $C$DW$38, DW_AT_location[DW_OP_regx 0x22]
     478                    $C$DW$39        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("IFR")
     479                            .dwattr $C$DW$39, DW_AT_location[DW_OP_regx 0x23]
     480                    $C$DW$40        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("NRP")
     481                            .dwattr $C$DW$40, DW_AT_location[DW_OP_regx 0x24]
     482                    $C$DW$41        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("A16")
     483                            .dwattr $C$DW$41, DW_AT_location[DW_OP_regx 0x25]
     484                    $C$DW$42        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("A17")
     485                            .dwattr $C$DW$42, DW_AT_location[DW_OP_regx 0x26]
     486                    $C$DW$43        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("A18")
     487                            .dwattr $C$DW$43, DW_AT_location[DW_OP_regx 0x27]
     488                    $C$DW$44        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("A19")
     489                            .dwattr $C$DW$44, DW_AT_location[DW_OP_regx 0x28]
     490                    $C$DW$45        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("A20")
     491                            .dwattr $C$DW$45, DW_AT_location[DW_OP_regx 0x29]
     492                    $C$DW$46        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("A21")
     493                            .dwattr $C$DW$46, DW_AT_location[DW_OP_regx 0x2a]
     494                    $C$DW$47        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("A22")
TMS320C6x Assembler PC v7.0.3 Thu Mar 17 15:38:40 2011

Tools Copyright (c) 1996-2010 Texas Instruments Incorporated
CT610dspMain.asm                                                     PAGE   10

     495                            .dwattr $C$DW$47, DW_AT_location[DW_OP_regx 0x2b]
     496                    $C$DW$48        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("A23")
     497                            .dwattr $C$DW$48, DW_AT_location[DW_OP_regx 0x2c]
     498                    $C$DW$49        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("A24")
     499                            .dwattr $C$DW$49, DW_AT_location[DW_OP_regx 0x2d]
     500                    $C$DW$50        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("A25")
     501                            .dwattr $C$DW$50, DW_AT_location[DW_OP_regx 0x2e]
     502                    $C$DW$51        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("A26")
     503                            .dwattr $C$DW$51, DW_AT_location[DW_OP_regx 0x2f]
     504                    $C$DW$52        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("A27")
     505                            .dwattr $C$DW$52, DW_AT_location[DW_OP_regx 0x30]
     506                    $C$DW$53        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("A28")
     507                            .dwattr $C$DW$53, DW_AT_location[DW_OP_regx 0x31]
     508                    $C$DW$54        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("A29")
     509                            .dwattr $C$DW$54, DW_AT_location[DW_OP_regx 0x32]
     510                    $C$DW$55        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("A30")
     511                            .dwattr $C$DW$55, DW_AT_location[DW_OP_regx 0x33]
     512                    $C$DW$56        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("A31")
     513                            .dwattr $C$DW$56, DW_AT_location[DW_OP_regx 0x34]
     514                    $C$DW$57        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("B16")
     515                            .dwattr $C$DW$57, DW_AT_location[DW_OP_regx 0x35]
     516                    $C$DW$58        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("B17")
     517                            .dwattr $C$DW$58, DW_AT_location[DW_OP_regx 0x36]
     518                    $C$DW$59        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("B18")
     519                            .dwattr $C$DW$59, DW_AT_location[DW_OP_regx 0x37]
     520                    $C$DW$60        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("B19")
     521                            .dwattr $C$DW$60, DW_AT_location[DW_OP_regx 0x38]
     522                    $C$DW$61        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("B20")
     523                            .dwattr $C$DW$61, DW_AT_location[DW_OP_regx 0x39]
     524                    $C$DW$62        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("B21")
     525                            .dwattr $C$DW$62, DW_AT_location[DW_OP_regx 0x3a]
     526                    $C$DW$63        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("B22")
     527                            .dwattr $C$DW$63, DW_AT_location[DW_OP_regx 0x3b]
     528                    $C$DW$64        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("B23")
     529                            .dwattr $C$DW$64, DW_AT_location[DW_OP_regx 0x3c]
     530                    $C$DW$65        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("B24")
     531                            .dwattr $C$DW$65, DW_AT_location[DW_OP_regx 0x3d]
     532                    $C$DW$66        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("B25")
     533                            .dwattr $C$DW$66, DW_AT_location[DW_OP_regx 0x3e]
     534                    $C$DW$67        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("B26")
     535                            .dwattr $C$DW$67, DW_AT_location[DW_OP_regx 0x3f]
     536                    $C$DW$68        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("B27")
     537                            .dwattr $C$DW$68, DW_AT_location[DW_OP_regx 0x40]
     538                    $C$DW$69        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("B28")
     539                            .dwattr $C$DW$69, DW_AT_location[DW_OP_regx 0x41]
     540                    $C$DW$70        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("B29")
     541                            .dwattr $C$DW$70, DW_AT_location[DW_OP_regx 0x42]
     542                    $C$DW$71        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("B30")
     543                            .dwattr $C$DW$71, DW_AT_location[DW_OP_regx 0x43]
     544                    $C$DW$72        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("B31")
     545                            .dwattr $C$DW$72, DW_AT_location[DW_OP_regx 0x44]
     546                    $C$DW$73        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("AMR")
     547                            .dwattr $C$DW$73, DW_AT_location[DW_OP_regx 0x45]
     548                    $C$DW$74        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("CSR")
     549                            .dwattr $C$DW$74, DW_AT_location[DW_OP_regx 0x46]
TMS320C6x Assembler PC v7.0.3 Thu Mar 17 15:38:40 2011

Tools Copyright (c) 1996-2010 Texas Instruments Incorporated
CT610dspMain.asm                                                     PAGE   11

     550                    $C$DW$75        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("ISR")
     551                            .dwattr $C$DW$75, DW_AT_location[DW_OP_regx 0x47]
     552                    $C$DW$76        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("ICR")
     553                            .dwattr $C$DW$76, DW_AT_location[DW_OP_regx 0x48]
     554                    $C$DW$77        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("IER")
     555                            .dwattr $C$DW$77, DW_AT_location[DW_OP_regx 0x49]
     556                    $C$DW$78        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("ISTP")
     557                            .dwattr $C$DW$78, DW_AT_location[DW_OP_regx 0x4a]
     558                    $C$DW$79        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("IN")
     559                            .dwattr $C$DW$79, DW_AT_location[DW_OP_regx 0x4b]
     560                    $C$DW$80        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("OUT")
     561                            .dwattr $C$DW$80, DW_AT_location[DW_OP_regx 0x4c]
     562                    $C$DW$81        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("ACR")
     563                            .dwattr $C$DW$81, DW_AT_location[DW_OP_regx 0x4d]
     564                    $C$DW$82        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("ADR")
     565                            .dwattr $C$DW$82, DW_AT_location[DW_OP_regx 0x4e]
     566                    $C$DW$83        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("FADCR")
     567                            .dwattr $C$DW$83, DW_AT_location[DW_OP_regx 0x4f]
     568                    $C$DW$84        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("FAUCR")
     569                            .dwattr $C$DW$84, DW_AT_location[DW_OP_regx 0x50]
     570                    $C$DW$85        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("FMCR")
     571                            .dwattr $C$DW$85, DW_AT_location[DW_OP_regx 0x51]
     572                    $C$DW$86        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("GFPGFR")
     573                            .dwattr $C$DW$86, DW_AT_location[DW_OP_regx 0x52]
     574                    $C$DW$87        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("DIER")
     575                            .dwattr $C$DW$87, DW_AT_location[DW_OP_regx 0x53]
     576                    $C$DW$88        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("REP")
     577                            .dwattr $C$DW$88, DW_AT_location[DW_OP_regx 0x54]
     578                    $C$DW$89        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("TSCL")
     579                            .dwattr $C$DW$89, DW_AT_location[DW_OP_regx 0x55]
     580                    $C$DW$90        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("TSCH")
     581                            .dwattr $C$DW$90, DW_AT_location[DW_OP_regx 0x56]
     582                    $C$DW$91        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("ARP")
     583                            .dwattr $C$DW$91, DW_AT_location[DW_OP_regx 0x57]
     584                    $C$DW$92        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("ILC")
     585                            .dwattr $C$DW$92, DW_AT_location[DW_OP_regx 0x58]
     586                    $C$DW$93        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("RILC")
     587                            .dwattr $C$DW$93, DW_AT_location[DW_OP_regx 0x59]
     588                    $C$DW$94        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("DNUM")
     589                            .dwattr $C$DW$94, DW_AT_location[DW_OP_regx 0x5a]
     590                    $C$DW$95        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("SSR")
     591                            .dwattr $C$DW$95, DW_AT_location[DW_OP_regx 0x5b]
     592                    $C$DW$96        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("GPLYA")
     593                            .dwattr $C$DW$96, DW_AT_location[DW_OP_regx 0x5c]
     594                    $C$DW$97        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("GPLYB")
     595                            .dwattr $C$DW$97, DW_AT_location[DW_OP_regx 0x5d]
     596                    $C$DW$98        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("TSR")
     597                            .dwattr $C$DW$98, DW_AT_location[DW_OP_regx 0x5e]
     598                    $C$DW$99        .dwtag  DW_TAG_TI_assign_register, DW_AT_name("ITSR")
     599                            .dwattr $C$DW$99, DW_AT_location[DW_OP_regx 0x5f]
     600                    $C$DW$100       .dwtag  DW_TAG_TI_assign_register, DW_AT_name("NTSR")
     601                            .dwattr $C$DW$100, DW_AT_location[DW_OP_regx 0x60]
     602                    $C$DW$101       .dwtag  DW_TAG_TI_assign_register, DW_AT_name("EFR")
     603                            .dwattr $C$DW$101, DW_AT_location[DW_OP_regx 0x61]
     604                    $C$DW$102       .dwtag  DW_TAG_TI_assign_register, DW_AT_name("ECR")
TMS320C6x Assembler PC v7.0.3 Thu Mar 17 15:38:40 2011

Tools Copyright (c) 1996-2010 Texas Instruments Incorporated
CT610dspMain.asm                                                     PAGE   12

     605                            .dwattr $C$DW$102, DW_AT_location[DW_OP_regx 0x62]
     606                    $C$DW$103       .dwtag  DW_TAG_TI_assign_register, DW_AT_name("IERR")
     607                            .dwattr $C$DW$103, DW_AT_location[DW_OP_regx 0x63]
     608                    $C$DW$104       .dwtag  DW_TAG_TI_assign_register, DW_AT_name("DMSG")
     609                            .dwattr $C$DW$104, DW_AT_location[DW_OP_regx 0x64]
     610                    $C$DW$105       .dwtag  DW_TAG_TI_assign_register, DW_AT_name("CMSG")
     611                            .dwattr $C$DW$105, DW_AT_location[DW_OP_regx 0x65]
     612                    $C$DW$106       .dwtag  DW_TAG_TI_assign_register, DW_AT_name("DT_DMA_ADDR")
     613                            .dwattr $C$DW$106, DW_AT_location[DW_OP_regx 0x66]
     614                    $C$DW$107       .dwtag  DW_TAG_TI_assign_register, DW_AT_name("DT_DMA_DATA")
     615                            .dwattr $C$DW$107, DW_AT_location[DW_OP_regx 0x67]
     616                    $C$DW$108       .dwtag  DW_TAG_TI_assign_register, DW_AT_name("DT_DMA_CNTL")
     617                            .dwattr $C$DW$108, DW_AT_location[DW_OP_regx 0x68]
     618                    $C$DW$109       .dwtag  DW_TAG_TI_assign_register, DW_AT_name("TCU_CNTL")
     619                            .dwattr $C$DW$109, DW_AT_location[DW_OP_regx 0x69]
     620                    $C$DW$110       .dwtag  DW_TAG_TI_assign_register, DW_AT_name("RTDX_REC_CNTL")
     621                            .dwattr $C$DW$110, DW_AT_location[DW_OP_regx 0x6a]
     622                    $C$DW$111       .dwtag  DW_TAG_TI_assign_register, DW_AT_name("RTDX_XMT_CNTL")
     623                            .dwattr $C$DW$111, DW_AT_location[DW_OP_regx 0x6b]
     624                    $C$DW$112       .dwtag  DW_TAG_TI_assign_register, DW_AT_name("RTDX_CFG")
     625                            .dwattr $C$DW$112, DW_AT_location[DW_OP_regx 0x6c]
     626                    $C$DW$113       .dwtag  DW_TAG_TI_assign_register, DW_AT_name("RTDX_RDATA")
     627                            .dwattr $C$DW$113, DW_AT_location[DW_OP_regx 0x6d]
     628                    $C$DW$114       .dwtag  DW_TAG_TI_assign_register, DW_AT_name("RTDX_WDATA")
     629                            .dwattr $C$DW$114, DW_AT_location[DW_OP_regx 0x6e]
     630                    $C$DW$115       .dwtag  DW_TAG_TI_assign_register, DW_AT_name("RTDX_RADDR")
     631                            .dwattr $C$DW$115, DW_AT_location[DW_OP_regx 0x6f]
     632                    $C$DW$116       .dwtag  DW_TAG_TI_assign_register, DW_AT_name("RTDX_WADDR")
     633                            .dwattr $C$DW$116, DW_AT_location[DW_OP_regx 0x70]
     634                    $C$DW$117       .dwtag  DW_TAG_TI_assign_register, DW_AT_name("MFREG0")
     635                            .dwattr $C$DW$117, DW_AT_location[DW_OP_regx 0x71]
     636                    $C$DW$118       .dwtag  DW_TAG_TI_assign_register, DW_AT_name("DBG_STAT")
     637                            .dwattr $C$DW$118, DW_AT_location[DW_OP_regx 0x72]
     638                    $C$DW$119       .dwtag  DW_TAG_TI_assign_register, DW_AT_name("BRK_EN")
     639                            .dwattr $C$DW$119, DW_AT_location[DW_OP_regx 0x73]
     640                    $C$DW$120       .dwtag  DW_TAG_TI_assign_register, DW_AT_name("HWBP0_CNT")
     641                            .dwattr $C$DW$120, DW_AT_location[DW_OP_regx 0x74]
     642                    $C$DW$121       .dwtag  DW_TAG_TI_assign_register, DW_AT_name("HWBP0")
     643                            .dwattr $C$DW$121, DW_AT_location[DW_OP_regx 0x75]
     644                    $C$DW$122       .dwtag  DW_TAG_TI_assign_register, DW_AT_name("HWBP1")
     645                            .dwattr $C$DW$122, DW_AT_location[DW_OP_regx 0x76]
     646                    $C$DW$123       .dwtag  DW_TAG_TI_assign_register, DW_AT_name("HWBP2")
     647                            .dwattr $C$DW$123, DW_AT_location[DW_OP_regx 0x77]
     648                    $C$DW$124       .dwtag  DW_TAG_TI_assign_register, DW_AT_name("HWBP3")
     649                            .dwattr $C$DW$124, DW_AT_location[DW_OP_regx 0x78]
     650                    $C$DW$125       .dwtag  DW_TAG_TI_assign_register, DW_AT_name("OVERLAY")
     651                            .dwattr $C$DW$125, DW_AT_location[DW_OP_regx 0x79]
     652                    $C$DW$126       .dwtag  DW_TAG_TI_assign_register, DW_AT_name("PC_PROF")
     653                            .dwattr $C$DW$126, DW_AT_location[DW_OP_regx 0x7a]
     654                    $C$DW$127       .dwtag  DW_TAG_TI_assign_register, DW_AT_name("ATSR")
     655                            .dwattr $C$DW$127, DW_AT_location[DW_OP_regx 0x7b]
     656                    $C$DW$128       .dwtag  DW_TAG_TI_assign_register, DW_AT_name("TRR")
     657                            .dwattr $C$DW$128, DW_AT_location[DW_OP_regx 0x7c]
     658                    $C$DW$129       .dwtag  DW_TAG_TI_assign_register, DW_AT_name("TCRR")
     659                            .dwattr $C$DW$129, DW_AT_location[DW_OP_regx 0x7d]
TMS320C6x Assembler PC v7.0.3 Thu Mar 17 15:38:40 2011

Tools Copyright (c) 1996-2010 Texas Instruments Incorporated
CT610dspMain.asm                                                     PAGE   13

     660                    $C$DW$130       .dwtag  DW_TAG_TI_assign_register, DW_AT_name("DESR")
     661                            .dwattr $C$DW$130, DW_AT_location[DW_OP_regx 0x7e]
     662                    $C$DW$131       .dwtag  DW_TAG_TI_assign_register, DW_AT_name("DETR")
     663                            .dwattr $C$DW$131, DW_AT_location[DW_OP_regx 0x7f]
     664                    $C$DW$132       .dwtag  DW_TAG_TI_assign_register, DW_AT_name("CIE_RETA")
     665                            .dwattr $C$DW$132, DW_AT_location[DW_OP_regx 0xe4]
     666                            .dwendtag $C$DW$CU
     667                   

No Assembly Errors, 1 Assembly Warning

Ron,

Ron Lingemann said:

I do not have an eval board. I can't see that it would make a difference. I am only trying to run code via the emulator. The code at this pont is only a C while loop executing NOPs, and an ASM set of interrupt vectors - almost nothing. I don't think my code is even relevant at htis point. The problem occurs in the code generated by th RTOS.

The evaluation board is important to rule out any possible hardware issues, therefore the question.

Ron Lingemann said:

It doesn't seem like the bootloader is relevant here, as it should be overidden by the JTAG control of the emulator.

When the bootloader is used, a mistake in certain parameters could cause the application to be loaded to the internal device memory in a twisted way similarly to what you reported. As you confirmed you are loading the code via the emulator, this shouldn't happen. 

Ron Lingemann said:

I have done a number of succesful projects using 280x, 550x, and MSPs, but this is the first using the 6xxx series. I have probed the JTAG interface with a low C probe, and the signals look good. I believe that if there was a problem with the hardware, execution of the gel would show it, as the gel has several wait loops in it that complete.

Most of the devices in the C6x family have bi-endianess (defined by a sampled pin at power-up) but, as I mentioned before, this would cause the entire 32-bit word to be swapped (and not only the 16-bit pairs).

Unless there is a detail on the hardware that I am missing, the GEL file should not influence the memory configuration. In any case, could you send the GEL file you are using just to confirm?
 

Ron Lingemann said:

I've not been able to attach files through this website, so I've loaded the text of the map and lst files here. If you can give me a direct email, I'll try to send the files there.

Check the friend request I sent.

Cheers,
Rafael

Hi Rafael,

The gel file has been appended below. I have tried loading a file with the gel file dissabled. The result was exactly the same.

When I enable the gel file, it runs without a problem. This leads me to believe that the emulator is loading correct data form the gel file and executing properly.

If the code .out file is disassembled using dis6x, the code makes sense. This leads me to believe that the compiler, assembler, and linker are working properly.

I have set the project properties to default values, so I do not believe the problem is there.

It looks to me like the CCS4 software loading commands to the target for the gel interface is different from the software loading the code from the .out file, and that the problem is in the loader.

The system is running CCS4.2.1.00004 on a PC using Win XP SP3 and a Spectrum Digital XDS100V2 emulator with the current CPLD update.

// CT-610 GEL File for C6745 - Reduced from TTO.gel for OPAM137 Eval board (conflicting lines have been commented out)

#define PLL0_BASE       0x01C11000                              /*SYSTEM PLL BASE ADDRESS*/
#define PLL0_PID        *(unsigned int*) (PLL0_BASE + 0x00)     /*PID*/
#define PLL0_RSTYPE     *(unsigned int*) (PLL0_BASE + 0xE4)     /*Reset Type status Reg*/
#define PLL0_PLLCTL     *(unsigned int*) (PLL0_BASE + 0x100)    /*PLL Control Register*/
#define PLL0_OCSEL      *(unsigned int*) (PLL0_BASE + 0x104)    /*OBSCLK Select Register*/
#define PLL0_SECCTL     *(unsigned int*) (PLL0_BASE + 0x108)    /*PLL Secondary Control Register*/
#define PLL0_PLLM       *(unsigned int*) (PLL0_BASE + 0x110)    /*PLL Multiplier*/
#define PLL0_PREDIV     *(unsigned int*) (PLL0_BASE + 0x114)    /*Pre divider*/
#define PLL0_PLLDIV1    *(unsigned int*) (PLL0_BASE + 0x118)    /*Divider-1*/
#define PLL0_PLLDIV2    *(unsigned int*) (PLL0_BASE + 0x11C)    /*Divider-2*/
#define PLL0_PLLDIV3    *(unsigned int*) (PLL0_BASE + 0x120)    /*Divider-3*/
#define PLL0_OSCDIV1    *(unsigned int*) (PLL0_BASE + 0x124)    /*Oscilator Divider*/
#define PLL0_POSTDIV    *(unsigned int*) (PLL0_BASE + 0x128)    /*Post Divider*/
#define PLL0_BPDIV      *(unsigned int*) (PLL0_BASE + 0x12C)    /*Bypass Divider*/
#define PLL0_WAKEUP     *(unsigned int*) (PLL0_BASE + 0x130)    /*Wakeup Reg*/
#define PLL0_PLLCMD     *(unsigned int*) (PLL0_BASE + 0x138)    /*Command Reg*/
#define PLL0_PLLSTAT    *(unsigned int*) (PLL0_BASE + 0x13C)    /*Status Reg*/
#define PLL0_ALNCTL     *(unsigned int*) (PLL0_BASE + 0x140)    /*Clock Align Control Reg*/
#define PLL0_DCHANGE    *(unsigned int*) (PLL0_BASE + 0x144)    /*PLLDIV Ratio Chnage status*/
#define PLL0_CKEN       *(unsigned int*) (PLL0_BASE + 0x148)    /*Clock Enable Reg*/
#define PLL0_CKSTAT     *(unsigned int*) (PLL0_BASE + 0x14C)    /*Clock Status Reg*/
#define PLL0_SYSTAT     *(unsigned int*) (PLL0_BASE + 0x150)    /*Sysclk status reg*/
#define PLL0_PLLDIV4    *(unsigned int*) (PLL0_BASE + 0x160)    /*Divider 4*/
#define PLL0_PLLDIV5    *(unsigned int*) (PLL0_BASE + 0x164)    /*Divider 5*/
#define PLL0_PLLDIV6    *(unsigned int*) (PLL0_BASE + 0x168)    /*Divider 6*/
#define PLL0_PLLDIV7    *(unsigned int*) (PLL0_BASE + 0x16C)    /*Divider 7*/
#define PLL0_PLLDIV8    *(unsigned int*) (PLL0_BASE + 0x170)    /*Divider 8*/
#define PLL0_PLLDIV9    *(unsigned int*) (PLL0_BASE + 0x174)    /*Divider 9*/
#define PLL0_PLLDIV10   *(unsigned int*) (PLL0_BASE + 0x178)    /*Divider 10*/
#define PLL0_PLLDIV11   *(unsigned int*) (PLL0_BASE + 0x17C)    /*Divider 11*/
#define PLL0_PLLDIV12   *(unsigned int*) (PLL0_BASE + 0x180)    /*Divider 12*/
#define PLL0_PLLDIV13   *(unsigned int*) (PLL0_BASE + 0x184)    /*Divider 13*/
#define PLL0_PLLDIV14   *(unsigned int*) (PLL0_BASE + 0x188)    /*Divider 14*/
#define PLL0_PLLDIV15   *(unsigned int*) (PLL0_BASE + 0x18C)    /*Divider 15*/
#define PLL0_PLLDIV16   *(unsigned int*) (PLL0_BASE + 0x190)    /*Divider 16*/

#define PLL1_BASE       0x01E1A000                              /*SYSTEM PLL1 BASE ADDRESS*/
#define PLL1_PID        *(unsigned int*) (PLL1_BASE + 0x00)     /*PID*/
#define PLL1_RSTYPE     *(unsigned int*) (PLL1_BASE + 0xE4)     /*Reset Type status Reg*/
#define PLL1_PLLCTL     *(unsigned int*) (PLL1_BASE + 0x100)    /*PLL Control Register*/
#define PLL1_OCSEL      *(unsigned int*) (PLL1_BASE + 0x104)    /*OBSCLK Select Register*/
#define PLL1_SECCTL     *(unsigned int*) (PLL1_BASE + 0x108)    /*PLL Secondary Control Register*/
#define PLL1_PLLM       *(unsigned int*) (PLL1_BASE + 0x110)    /*PLL Multiplier*/
#define PLL1_PREDIV     *(unsigned int*) (PLL1_BASE + 0x114)    /*Pre divider*/
#define PLL1_PLLDIV1    *(unsigned int*) (PLL1_BASE + 0x118)    /*Divider-1*/
#define PLL1_PLLDIV2    *(unsigned int*) (PLL1_BASE + 0x11C)    /*Divider-2*/
#define PLL1_PLLDIV3    *(unsigned int*) (PLL1_BASE + 0x120)    /*Divider-3*/
#define PLL1_OSCDIV1    *(unsigned int*) (PLL1_BASE + 0x124)    /*Oscilator Divider*/
#define PLL1_POSTDIV    *(unsigned int*) (PLL1_BASE + 0x128)    /*Post Divider*/
#define PLL1_BPDIV      *(unsigned int*) (PLL1_BASE + 0x12C)    /*Bypass Divider*/
#define PLL1_WAKEUP     *(unsigned int*) (PLL1_BASE + 0x130)    /*Wakeup Reg*/
#define PLL1_PLLCMD     *(unsigned int*) (PLL1_BASE + 0x138)    /*Command Reg*/
#define PLL1_PLLSTAT    *(unsigned int*) (PLL1_BASE + 0x13C)    /*Status Reg*/
#define PLL1_ALNCTL     *(unsigned int*) (PLL1_BASE + 0x140)    /*Clock Align Control Reg*/
#define PLL1_DCHANGE    *(unsigned int*) (PLL1_BASE + 0x144)    /*PLLDIV Ratio Chnage status*/
#define PLL1_CKEN       *(unsigned int*) (PLL1_BASE + 0x148)    /*Clock Enable Reg*/
#define PLL1_CKSTAT     *(unsigned int*) (PLL1_BASE + 0x14C)    /*Clock Status Reg*/
#define PLL1_SYSTAT     *(unsigned int*) (PLL1_BASE + 0x150)    /*Sysclk status reg*/
#define PLL1_PLLDIV4    *(unsigned int*) (PLL1_BASE + 0x160)    /*Divider 4*/
#define PLL1_PLLDIV5    *(unsigned int*) (PLL1_BASE + 0x164)    /*Divider 5*/
#define PLL1_PLLDIV6    *(unsigned int*) (PLL1_BASE + 0x168)    /*Divider 6*/
#define PLL1_PLLDIV7    *(unsigned int*) (PLL1_BASE + 0x16C)    /*Divider 7*/
#define PLL1_PLLDIV8    *(unsigned int*) (PLL1_BASE + 0x170)    /*Divider 8*/
#define PLL1_PLLDIV9    *(unsigned int*) (PLL1_BASE + 0x174)    /*Divider 9*/
#define PLL1_PLLDIV10   *(unsigned int*) (PLL1_BASE + 0x178)    /*Divider 10*/
#define PLL1_PLLDIV11   *(unsigned int*) (PLL1_BASE + 0x17C)    /*Divider 11*/
#define PLL1_PLLDIV12   *(unsigned int*) (PLL1_BASE + 0x180)    /*Divider 12*/
#define PLL1_PLLDIV13   *(unsigned int*) (PLL1_BASE + 0x184)    /*Divider 13*/
#define PLL1_PLLDIV14   *(unsigned int*) (PLL1_BASE + 0x188)    /*Divider 14*/
#define PLL1_PLLDIV15   *(unsigned int*) (PLL1_BASE + 0x18C)    /*Divider 15*/
#define PLL1_PLLDIV16   *(unsigned int*) (PLL1_BASE + 0x190)    /*Divider 16*/

/*PSC Module Related Registers*/
#define PSC0_BASE       0x01C10000
#define PSC1_BASE       0x01E27000

#define PSC0_MDCTL      (PSC0_BASE+0xA00)
#define PSC0_MDSTAT     (PSC0_BASE+0x800)
#define PSC0_PTCMD      *(unsigned int*) (PSC0_BASE + 0x120)
#define PSC0_PTSTAT     *(unsigned int*) (PSC0_BASE + 0x128)

#define PSC1_MDCTL      (PSC1_BASE+0xA00)
#define PSC1_MDSTAT     (PSC1_BASE+0x800)
#define PSC1_PTCMD      *(unsigned int*) (PSC1_BASE + 0x120)
#define PSC1_PTSTAT     *(unsigned int*) (PSC1_BASE + 0x128)

#define PSC_TIMEOUT      200

#define LPSC_EDMA_CC0    0
#define LPSC_EDMA_TC0    1
#define LPSC_EDMA_TC1    2
#define LPSC_EMIFA       3   /*PSC0*/
#define LPSC_SPI0        4   /*PSC0*/
#define LPSC_MMCSD0      5   /*PSC0*/
#define LPSC_ARM_AINTC   6
#define LPSC_ARM_RAMROM  7   /*PSC0*/
// LPSC #8 not used
#define LPSC_UART0       9   /*PSC0*/
#define LPSC_SCR0        10
#define LPSC_SCR1        11
#define LPSC_SCR2        12
// LPSC #13 not used
#define LPSC_ARM         14  /*PSC0*/
#define LPSC_DSP         15  /*PSC0*/

#define LPSC_EDMA_CC1    0
#define LPSC_USB20       1   /*PSC1*/
#define LPSC_USB11       2   /*PSC1*/
#define LPSC_GPIO        3   /*PSC1*/
#define LPSC_UHPI        4   /*PSC1*/
#define LPSC_EMAC        5   /*PSC1*/
#define LPSC_DDR         6   /*PSC1*/
#define LPSC_MCASP0      7   /*PSC1*/
#define LPSC_SATA        8   /*PSC1*/
#define LPSC_VPIF        9   /*PSC1*/
#define LPSC_SPI1        10  /*PSC1*/
#define LPSC_I2C1        11  /*PSC1*/
#define LPSC_UART1       12  /*PSC1*/
#define LPSC_UART2       13  /*PSC1*/
#define LPSC_MCBSP0      14  /*PSC1*/
#define LPSC_MCBSP1      15  /*PSC1*/
#define LPSC_LCDC        16  /*PSC1*/
#define LPSC_EPWM        17  /*PSC1*/
#define LPSC_MMCSD1      18
#define LPSC_UPP         19
#define LPSC_ECAP        20
#define LPSC_EDMA_TC2    21
// LPSC #22-23 not used
#define LPSC_SCR_F0      24
#define LPSC_SCR_F1      25
#define LPSC_SCR_F2      26
#define LPSC_SCR_F6      27
#define LPSC_SCR_F7      28
#define LPSC_SCR_F8      29
#define LPSC_BR_F7       30
#define LPSC_SHARED_RAM  31

/*DDR MMR Declaration*/
#define VTPIO_CTL           *(unsigned int*)(0x01E2C000)                  // VTPIO_CTL Register
#define EMIFDDR_SDRAM_CFG   0xB0000000
#define EMIFDDR_REVID       *(unsigned int*)(EMIFDDR_SDRAM_CFG + 0x00)      //EMIF Module ID and Revision Register
#define EMIFDDR_SDRSTAT     *(unsigned int*)(EMIFDDR_SDRAM_CFG + 0x04)      //SDRAM Status Register
#define EMIFDDR_SDCR        *(unsigned int*)(EMIFDDR_SDRAM_CFG + 0x08)      //SDRAM Bank Config Register
#define EMIFDDR_SDRCR       *(unsigned int*)(EMIFDDR_SDRAM_CFG + 0x0C)      //SDRAM Refresh Control Register
#define EMIFDDR_SDTIMR1     *(unsigned int*)(EMIFDDR_SDRAM_CFG + 0x10)      //SDRAM Timing Register1
#define EMIFDDR_SDTIMR2     *(unsigned int*)(EMIFDDR_SDRAM_CFG + 0x14)      //SDRAM Timing Register2
#define EMIFDDR_SDCR2       *(unsigned int*)(EMIFDDR_SDRAM_CFG + 0x1C)      //SDRAM Config Register2
#define EMIFDDR_PBBPR       *(unsigned int*)(EMIFDDR_SDRAM_CFG + 0x20)      //VBUSM Burst Priority Register
#define EMIFDDR_VBUSMCFG1   *(unsigned int*)(EMIFDDR_SDRAM_CFG + 0x28)      //VBUSM config Value1 Register
#define EMIFDDR_VBUSMCFG2   *(unsigned int*)(EMIFDDR_SDRAM_CFG + 0x2C)      //VBUSM config Value2 Register
#define EMIFDDR_IRR         *(unsigned int*)(EMIFDDR_SDRAM_CFG + 0xC0)      //Interrupt Raw Register
#define EMIFDDR_IMR         *(unsigned int*)(EMIFDDR_SDRAM_CFG + 0xC4)      //Interrupt Masked Register
#define EMIFDDR_IMSR        *(unsigned int*)(EMIFDDR_SDRAM_CFG + 0xC8)      //Interrupt Mask Set Register
#define EMIFDDR_IMCR        *(unsigned int*)(EMIFDDR_SDRAM_CFG + 0xCC)      //Interrupt Mask Clear Register
#define DDRPHYREV           *(unsigned int*)(EMIFDDR_SDRAM_CFG + 0xE0)      //DDR PHY ID and Revision Register
#define DRPYC1R             *(unsigned int*)(EMIFDDR_SDRAM_CFG + 0xE4)      //DDR PHY Control 1 Register

#define DDR2 0
#define MDDR 1
#define VTP_TIMEOUT 200
#define DDR_DEBUG 0

#define EMIFDDR_BASE_ADDR       0xC0000000
#define EMIFA_BASE_ADDR         0x40000000
#define EMIFA_CS2_BASE_ADDR     0x60000000
#define EMIFA_CS3_BASE_ADDR     0x62000000
#define EMIFA_CS4_BASE_ADDR     0x64000000
#define EMIFA_CS5_BASE_ADDR     0x66000000

/*EMIF2.5 MMR Declaration*/
#define EMIFA             0x68000000

#define EMIFA_AWAITCFG    *(unsigned int*)(EMIFA + 0x04)
#define EMIFA_SDCFG       *(unsigned int*)(EMIFA + 0x08)
#define EMIFA_SDREF       *(unsigned int*)(EMIFA + 0x0C)
#define EMIFA_ACFG2       *(unsigned int*)(EMIFA + 0x10)    //Async Bank1 Config Register
#define EMIFA_ACFG3       *(unsigned int*)(EMIFA + 0x14)    //Async Bank2 Config Register
#define EMIFA_ACFG4       *(unsigned int*)(EMIFA + 0x18)    //Async Bank3 Config Register
#define EMIFA_ACFG5       *(unsigned int*)(EMIFA + 0x1C)    //Async Bank4 Config Register
#define EMIFA_SDTIM       *(unsigned int*)(EMIFA + 0x20)    //SDRAM Timing Register
#define EMIFA_SRPD        *(unsigned int*)(EMIFA + 0x3C)
#define EMIFA_NANDFCR     *(unsigned int*)(EMIFA + 0x60)

/*GPIO MMR*/
#define GPIO_REG_BASE         (0x01E26000)
#define GPIO_BANK_OFFSET      (0x28)
#define GPIO_DAT_OFFSET       (0x04)
#define GPIO_SET_OFFSET       (0x08)
#define GPIO_CLR_OFFSET       (0x0C)
#define GPIO_BINTEN           *(unsigned int*)(GPIO_REG_BASE + 0x08)
#define GPIO_BANK01_BASE      (GPIO_REG_BASE + 0x10)
#define GPIO_BANK23_BASE      (GPIO_BANK01_BASE + GPIO_BANK_OFFSET)
#define GPIO_BANK45_BASE      (GPIO_BANK23_BASE + GPIO_BANK_OFFSET)
#define GPIO_BANK67_BASE      (GPIO_BANK45_BASE + GPIO_BANK_OFFSET)
#define GPIO_BANK8_BASE       (GPIO_BANK67_BASE + GPIO_BANK_OFFSET)
#define GPIO_BANK23_DIR       *(unsigned int*)(GPIO_BANK23_BASE)
#define GPIO_BANK23_DAT       *(unsigned int*)(GPIO_BANK23_BASE + GPIO_DAT_OFFSET)
#define GPIO_BANK23_SET       *(unsigned int*)(GPIO_BANK23_BASE + GPIO_SET_OFFSET)
#define GPIO_BANK23_CLR       *(unsigned int*)(GPIO_BANK23_BASE + GPIO_CLR_OFFSET)

/*System MMR Declaration*/
#define SYS_BASE           0x01C14000
#define HOST0CFG           *(unsigned int*)(SYS_BASE + 0x040)  //ARM HOST0CFG
#define KICK0R             *(unsigned int*)(SYS_BASE + 0x038)
#define KICK1R             *(unsigned int*)(SYS_BASE + 0x03c)
#define PINMUX0            *(unsigned int*)(SYS_BASE + 0x120)  //PINMUX0
#define PINMUX1            *(unsigned int*)(SYS_BASE + 0x124)  //PINMUX1
#define PINMUX2            *(unsigned int*)(SYS_BASE + 0x128)  //PINMUX2
#define PINMUX3            *(unsigned int*)(SYS_BASE + 0x12C)  //PINMUX3
#define PINMUX4            *(unsigned int*)(SYS_BASE + 0x130)  //PINMUX4
#define PINMUX5            *(unsigned int*)(SYS_BASE + 0x134)  //PINMUX5
#define PINMUX6            *(unsigned int*)(SYS_BASE + 0x138)  //PINMUX6
#define PINMUX7            *(unsigned int*)(SYS_BASE + 0x13C)  //PINMUX7
#define PINMUX8            *(unsigned int*)(SYS_BASE + 0x140)  //PINMUX8
#define PINMUX9            *(unsigned int*)(SYS_BASE + 0x144)  //PINMUX9
#define PINMUX10           *(unsigned int*)(SYS_BASE + 0x148)  //PINMUX10
#define PINMUX11           *(unsigned int*)(SYS_BASE + 0x14C)  //PINMUX11
#define PINMUX12           *(unsigned int*)(SYS_BASE + 0x150)  //PINMUX12
#define PINMUX13           *(unsigned int*)(SYS_BASE + 0x154)  //PINMUX13
#define PINMUX14           *(unsigned int*)(SYS_BASE + 0x158)  //PINMUX14
#define PINMUX15           *(unsigned int*)(SYS_BASE + 0x15C)  //PINMUX15
#define PINMUX16           *(unsigned int*)(SYS_BASE + 0x160)  //PINMUX16
#define PINMUX17           *(unsigned int*)(SYS_BASE + 0x164)  //PINMUX17
#define PINMUX18           *(unsigned int*)(SYS_BASE + 0x168)  //PINMUX18
#define PINMUX19           *(unsigned int*)(SYS_BASE + 0x16C)  //PINMUX19
#define CFGCHIP0           *(unsigned int*)(SYS_BASE + 0x17C)
#define CFGCHIP2           *(unsigned int*)(SYS_BASE + 0x184)
#define CFGCHIP3           *(unsigned int*)(SYS_BASE + 0x188)
#define PD0                0   /*Power Domain-0*/
#define PD1                1   /*Power Domain-1*/

#define PLLEN_MUX_SWITCH         4
#define PLL_LOCK_TIME_CNT        2400
#define PLL_STABILIZATION_TIME   2000
#define PLL_RESET_TIME_CNT       200

OnTargetConnect( )
{
    Clear_Memory_Map();
    Setup_Memory_Map();

    PSC_All_On_Full_EVM();
    Core_300MHz_mDDR_150MHz();
    Wake_DSP();
// GEL_Halt();
// GEL_Reset();
}

menuitem "Wake Core"
hotmenu Wake_DSP()
{
    PSC0_LPSC_enableCore(1, LPSC_DSP);

    GEL_TextOut("\tDSP Wake Complete.\n","Output",1,1,1);
    GEL_TextOut("\t---------------------------------------------\n","Output",1,1,1);
}

menuitem "OMAP-L138 Memory Map"
/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  Clear_Memory_Map( )                                                     *
 *      Clear the Memory Map                                                *
 *                                                                          *
 * ------------------------------------------------------------------------ */
hotmenu Clear_Memory_Map()
{
    GEL_MapOff( );
    GEL_MapReset( );
    GEL_TextOut("\tMemory Map Cleared.\n","Output",1,1,1);
    GEL_TextOut("\t---------------------------------------------\n","Output",1,1,1);
}

hotmenu Setup_Memory_Map()
{
    GEL_MapOn( );
    GEL_MapReset( );

    /* ARM */
//    GEL_MapAddStr( 0xFFFD0000, 0, 0x00010000, "R|W|AS4", 0 );   // ARM Local ROM
//    GEL_MapAddStr( 0xFFFE0000, 0, 0x00002000, "R|W|AS4", 0 );   // ARM INTC
//    GEL_MapAddStr( 0xFFFF0000, 0, 0x00002000, "R|W|AS4", 0 );   // ARM Local RAM
//    GEL_MapAddStr( 0x01BC0000, 0, 0x00001000, "R|W|AS4", 0 );   // ARM ETB Memory
//    GEL_MapAddStr( 0x01BC1000, 0, 0x00000800, "R|W|AS4", 0 );   // ARM ETB Regs
//    GEL_MapAddStr( 0x01BC1800, 0, 0x00000100, "R|W|AS4", 0 );   // ARM Ice Crusher

    /* DSP */
    GEL_MapAddStr( 0x00700000, 0, 0x00100000, "R|W|AS4", 0 );   // DSP L2 ROM
    GEL_MapAddStr( 0x00800000, 0, 0x00040000, "R|W|AS4", 0 );   // DSP l2 RAM
    GEL_MapAddStr( 0x00E00000, 0, 0x00008000, "R|W|AS4", 0 );   // DSP L1P RAM
    GEL_MapAddStr( 0x00F00000, 0, 0x00008000, "R|W|AS4", 0 );   // DSP L1D RAM
    GEL_MapAddStr( 0x01800000, 0, 0x00010000, "R|W|AS4", 0 );   // DSP Interrupt Controller
    GEL_MapAddStr( 0x01810000, 0, 0x00001000, "R|W|AS4", 0 );   // DSP Powerdown Controller
    GEL_MapAddStr( 0x01811000, 0, 0x00001000, "R|W|AS4", 0 );   // DSP Security ID
    GEL_MapAddStr( 0x01812000, 0, 0x00008000, "R|W|AS4", 0 );   // DSP Revision ID
    GEL_MapAddStr( 0x01820000, 0, 0x00010000, "R|W|AS4", 0 );   // DSP EMC
    GEL_MapAddStr( 0x01830000, 0, 0x00010000, "R|W|AS4", 0 );   // DSP Internal Reserved
    GEL_MapAddStr( 0x01840000, 0, 0x00010000, "R|W|AS4", 0 );   // DSP Memory System

    GEL_MapAddStr( 0x11700000, 0, 0x00100000, "R|W|AS4", 0 );   // DSP L2 ROM (mirror)
    GEL_MapAddStr( 0x11800000, 0, 0x00040000, "R|W|AS4", 0 );   // DSP l2 RAM (mirror)
    GEL_MapAddStr( 0x11E00000, 0, 0x00008000, "R|W|AS4", 0 );   // DSP L1P RAM (mirror)
    GEL_MapAddStr( 0x11F00000, 0, 0x00008000, "R|W|AS4", 0 );   // DSP L1D RAM (mirror)
 
    /* Shared RAM */
//    GEL_MapAddStr( 0x80000000, 0, 0x00020000, "R|W|AS4", 0 );   // Shared RAM

    /* EMIFA */
    GEL_MapAddStr( 0x40000000, 0, 0x20000000, "R|W|AS4", 0 );   // EMIFA SDRAM Data
    GEL_MapAddStr( 0x60000000, 0, 0x02000000, "R|W|AS4", 0 );   // EMIFA CS2
    GEL_MapAddStr( 0x62000000, 0, 0x02000000, "R|W|AS4", 0 );   // EMIFA CS3
    GEL_MapAddStr( 0x64000000, 0, 0x02000000, "R|W|AS4", 0 );   // EMIFA CS4
    GEL_MapAddStr( 0x66000000, 0, 0x02000000, "R|W|AS4", 0 );   // EMIFA CS5
    GEL_MapAddStr( 0x68000000, 0, 0x00008000, "R|W|AS4", 0 );   // EMIFA Control

    /* DDR */
    GEL_MapAddStr( 0xB0000000, 0, 0x00008000, "R|W|AS4", 0 );   // DDR Control
    GEL_MapAddStr( 0xC0000000, 0, 0x20000000, "R|W|AS4", 0 );   // DDR Data

    /* Peripherals */
    GEL_MapAddStr( 0x01C00000, 0, 0x00008000, "R|W|AS4", 0 );   // TPCC0
    GEL_MapAddStr( 0x01C08000, 0, 0x00000400, "R|W|AS4", 0 );   // TPTC0
    GEL_MapAddStr( 0x01C08400, 0, 0x00000400, "R|W|AS4", 0 );   // TPTC1
    GEL_MapAddStr( 0x01C10000, 0, 0x00001000, "R|W|AS4", 0 );   // PSC 0
    GEL_MapAddStr( 0x01C11000, 0, 0x00001000, "R|W|AS4", 0 );   // PLL Controller 0
    GEL_MapAddStr( 0x01C12000, 0, 0x00001000, "R|W|AS4", 0 );   // Key Manager
    GEL_MapAddStr( 0x01C13000, 0, 0x00001000, "R|W|AS4", 0 );   // SecCo
    GEL_MapAddStr( 0x01C14000, 0, 0x00001000, "R|W|AS4", 0 );   // SysConfig
    GEL_MapAddStr( 0x01C16000, 0, 0x00001000, "R|W|AS4", 0 );   // IOPU 0
    GEL_MapAddStr( 0x01C17000, 0, 0x00001000, "R|W|AS4", 0 );   // IOPU 2
    GEL_MapAddStr( 0x01C20000, 0, 0x00001000, "R|W|AS4", 0 );   // Timer64P 0
    GEL_MapAddStr( 0x01C21000, 0, 0x00001000, "R|W|AS4", 0 );   // Timer64P 1
    GEL_MapAddStr( 0x01C22000, 0, 0x00001000, "R|W|AS4", 0 );   // I2C 0
    GEL_MapAddStr( 0x01C23000, 0, 0x00001000, "R|W|AS4", 0 );   // RTC
    GEL_MapAddStr( 0x01C24000, 0, 0x00001000, "R|W|AS4", 0 );   // IOPU 1
    GEL_MapAddStr( 0x01C30000, 0, 0x00000200, "R|W|AS4", 0 );   // PRU Data RAM 0
    GEL_MapAddStr( 0x01C32000, 0, 0x00000200, "R|W|AS4", 0 );   // PRU Data RAM 1
    GEL_MapAddStr( 0x01C34000, 0, 0x00004000, "R|W|AS4", 0 );   // PRU Control Registers
    GEL_MapAddStr( 0x01C38000, 0, 0x00001000, "R|W|AS4", 0 );   // PRU 0 Config Memory
    GEL_MapAddStr( 0x01C3C000, 0, 0x00001000, "R|W|AS4", 0 );   // PRU 1 Config Memory
    GEL_MapAddStr( 0x01C40000, 0, 0x00001000, "R|W|AS4", 0 );   // MMC/SD 0
    GEL_MapAddStr( 0x01C41000, 0, 0x00001000, "R|W|AS4", 0 );   // SPI 0
    GEL_MapAddStr( 0x01C42000, 0, 0x00001000, "R|W|AS4", 0 );   // UART 0
    GEL_MapAddStr( 0x01C43000, 0, 0x00001000, "R|W|AS4", 0 );   // MPU 0
    GEL_MapAddStr( 0x01D00000, 0, 0x00001000, "R|W|AS4", 0 );   // McASP 0 Control
    GEL_MapAddStr( 0x01D01000, 0, 0x00001000, "R|W|AS4", 0 );   // McASP 0 FIFO Ctrl
    GEL_MapAddStr( 0x01D02000, 0, 0x00001000, "R|W|AS4", 0 );   // McASP 0 Data
    GEL_MapAddStr( 0x01D0C000, 0, 0x00001000, "R|W|AS4", 0 );   // UART 1
    GEL_MapAddStr( 0x01D0D000, 0, 0x00001000, "R|W|AS4", 0 );   // UART 2
    GEL_MapAddStr( 0x01D0E000, 0, 0x00001000, "R|W|AS4", 0 );   // IOPU 4
    GEL_MapAddStr( 0x01D10000, 0, 0x00000800, "R|W|AS4", 0 );   // McBSP 0 Control
    GEL_MapAddStr( 0x01D10800, 0, 0x00000200, "R|W|AS4", 0 );   // McBSP 0 FIFO Ctrl
    GEL_MapAddStr( 0x01D11000, 0, 0x00000800, "R|W|AS4", 0 );   // McBSP 1 Control
    GEL_MapAddStr( 0x01D11800, 0, 0x00000200, "R|W|AS4", 0 );   // McBSP 1 FIFO Ctrl
    GEL_MapAddStr( 0x01E00000, 0, 0x00010000, "R|W|AS4", 0 );   // USB0 (USB HS) Cfg
    GEL_MapAddStr( 0x01E10000, 0, 0x00001000, "R|W|AS4", 0 );   // UHPI Cfg
    GEL_MapAddStr( 0x01E11000, 0, 0x00001000, "R|W|AS4", 0 );   // UHPI (IODFT)
    GEL_MapAddStr( 0x01E13000, 0, 0x00001000, "R|W|AS4", 0 );   // LCD Controller
    GEL_MapAddStr( 0x01E14000, 0, 0x00001000, "R|W|AS4", 0 );   // MPU 1
    GEL_MapAddStr( 0x01E15000, 0, 0x00001000, "R|W|AS4", 0 );   // MPU 2
    GEL_MapAddStr( 0x01E16000, 0, 0x00001000, "R|W|AS4", 0 );   // UPP
    GEL_MapAddStr( 0x01E17000, 0, 0x00001000, "R|W|AS4", 0 );   // VPIF
    GEL_MapAddStr( 0x01E18000, 0, 0x00002000, "R|W|AS4", 0 );   // SATA
    GEL_MapAddStr( 0x01E1A000, 0, 0x00001000, "R|W|AS4", 0 );   // PLL Controller 1
    GEL_MapAddStr( 0x01E1B000, 0, 0x00001000, "R|W|AS4", 0 );   // MMC/SD 1
    GEL_MapAddStr( 0x01E20000, 0, 0x00002000, "R|W|AS4", 0 );   // EMAC CPPI
    GEL_MapAddStr( 0x01E22000, 0, 0x00001000, "R|W|AS4", 0 );   // EMAC CONTROL registers
    GEL_MapAddStr( 0x01E23000, 0, 0x00001000, "R|W|AS4", 0 );   // EMAC registers
    GEL_MapAddStr( 0x01E24000, 0, 0x00001000, "R|W|AS4", 0 );   // EMAC MDIO port
    GEL_MapAddStr( 0x01E25000, 0, 0x00001000, "R|W|AS4", 0 );   // USB1 (USB FS)
    GEL_MapAddStr( 0x01E26000, 0, 0x00001000, "R|W|AS4", 0 );   // GPIO
    GEL_MapAddStr( 0x01E27000, 0, 0x00001000, "R|W|AS4", 0 );   // PSC 1
    GEL_MapAddStr( 0x01E28000, 0, 0x00001000, "R|W|AS4", 0 );   // I2C 1
    GEL_MapAddStr( 0x01E29000, 0, 0x00001000, "R|W|AS4", 0 );   // IOPU 3
    GEL_MapAddStr( 0x01E2A000, 0, 0x00001000, "R|W|AS4", 0 );   // PBIST Controller
    GEL_MapAddStr( 0x01E2B000, 0, 0x00001000, "R|W|AS4", 0 );   // PBIST Combiner
    GEL_MapAddStr( 0x01E2C000, 0, 0x00001000, "R|W|AS4", 0 );   // System Config

    GEL_MapAddStr( 0x01E30000, 0, 0x00008000, "R|W|AS4", 0 );   // TPCC1
    GEL_MapAddStr( 0x01E38000, 0, 0x00000400, "R|W|AS4", 0 );   // TPTC2
    GEL_MapAddStr( 0x01F00000, 0, 0x00001000, "R|W|AS4", 0 );   // EPWM 0
    GEL_MapAddStr( 0x01F01000, 0, 0x00001000, "R|W|AS4", 0 );   // HRPWM 0
    GEL_MapAddStr( 0x01F02000, 0, 0x00001000, "R|W|AS4", 0 );   // EPWM 1
    GEL_MapAddStr( 0x01F03000, 0, 0x00001000, "R|W|AS4", 0 );   // HRPWM 1
    GEL_MapAddStr( 0x01F06000, 0, 0x00001000, "R|W|AS4", 0 );   // ECAP 0
    GEL_MapAddStr( 0x01F07000, 0, 0x00001000, "R|W|AS4", 0 );   // ECAP 1
    GEL_MapAddStr( 0x01F08000, 0, 0x00001000, "R|W|AS4", 0 );   // ECAP 2
    GEL_MapAddStr( 0x01F0B000, 0, 0x00001000, "R|W|AS4", 0 );   // IOPU 5
    GEL_MapAddStr( 0x01F0C000, 0, 0x00001000, "R|W|AS4", 0 );   // Timer64P 2
    GEL_MapAddStr( 0x01F0D000, 0, 0x00001000, "R|W|AS4", 0 );   // Timer64P 3
    GEL_MapAddStr( 0x01F0E000, 0, 0x00001000, "R|W|AS4", 0 );   // SPI1
    GEL_MapAddStr( 0x01F10000, 0, 0x00001000, "R|W|AS4", 0 );   // McBSP 0 FIFO Data
    GEL_MapAddStr( 0x01F11000, 0, 0x00001000, "R|W|AS4", 0 );   // McBSP 1 FIFO Data
    GEL_TextOut("\tMemory Map Setup Complete.\n","Output",1,1,1);
    GEL_TextOut("\t---------------------------------------------\n","Output",1,1,1);
}

Set_Core_300MHz() {
    device_PLL0(0,24,1,0,1,11,5);
    GEL_TextOut("\tPLL0 init done for Core:300MHz, EMIFA:25MHz\n","Output",1,1,1);
}
Set_Core_200MHz() {
    device_PLL0(0,24,2,0,1,7,3);
    GEL_TextOut("\tPLL0 init done for Core:200MHz, EMIFA:25MHz\n","Output",1,1,1);
}
Set_Core_100MHz() {
    device_PLL0(0,24,5,0,1,3,1);
    GEL_TextOut("\tPLL0 init done for Core:100MHz, EMIFA:25MHz\n","Output",1,1,1);
}

Set_DDRPLL_150MHz() {
    device_PLL1(24,1,0,1,2);
    GEL_TextOut("\tPLL1 init done for DDR:150MHz\n","Output",1,1,1);
}
Set_DDRPLL_132MHz() {
    device_PLL1(21,1,0,1,2);
    GEL_TextOut("\tPLL1 init done for DDR:132MHz\n","Output",1,1,1);
}
Set_DDRPLL_126MHz() {
    device_PLL1(20,1,0,1,2);
    GEL_TextOut("\tPLL1 init done for DDR:126MHz\n","Output",1,1,1);
}
Set_DDRPLL_102MHz() {
    device_PLL1(16,1,0,1,2);
    GEL_TextOut("\tPLL1 init done for DDR:102MHz\n","Output",1,1,1);
}

Set_mDDR_150MHz() {
    GEL_TextOut("\tmDDR initialization is in progress....\n","Output",1,1,1);
    Set_DDRPLL_150MHz();
    DEVICE_DDRConfig(MDDR, 150);
    GEL_TextOut("\tmDDR init for 150 MHz is done\n","Output",1,1,1);
}

Set_mDDR_132MHz() {
    GEL_TextOut("\tmDDR initialization is in progress....\n","Output",1,1,1);
    Set_DDRPLL_132MHz();
    DEVICE_DDRConfig(MDDR, 132);
    GEL_TextOut("\tmDDR init for 132 MHz is done\n","Output",1,1,1);
}

Set_mDDR_126MHz() {
    GEL_TextOut("\tmDDR initialization is in progress....\n","Output",1,1,1);
    Set_DDRPLL_126MHz();
    DEVICE_DDRConfig(MDDR, 126);
    GEL_TextOut("\tmDDR init for 126 MHz is done\n","Output",1,1,1);
}

Set_mDDR_102MHz() {
    GEL_TextOut("\tmDDR initialization is in progress....\n","Output",1,1,1);
    Set_DDRPLL_102MHz();
    DEVICE_DDRConfig(MDDR, 102);
    GEL_TextOut("\tmDDR init for 102 MHz is done\n","Output",1,1,1);
}

menuitem "Frequency Settings"
hotmenu Core_300MHz_mDDR_150MHz() {
    Set_Core_300MHz();
    Set_mDDR_150MHz();
    GEL_TextOut("\t---------------------------------------------\n","Output",1,1,1);
}

hotmenu Core_300MHz_mDDR_132MHz() {
    Set_Core_300MHz();
    Set_mDDR_132MHz();
    GEL_TextOut("\t---------------------------------------------\n","Output",1,1,1);
}

hotmenu Core_200MHz_mDDR_126MHz() {
    Set_Core_200MHz();
    Set_mDDR_126MHz();
    GEL_TextOut("\t---------------------------------------------\n","Output",1,1,1);
}

hotmenu Core_100MHz_mDDR_102MHz() {
    Set_Core_100MHz();
    Set_mDDR_102MHz();
    GEL_TextOut("\t---------------------------------------------\n","Output",1,1,1);
}

menuitem "Experimenter"

hotmenu PSC_All_On_Experimenter() {
    GEL_TextOut("\tEnabling Experimenter PSCs...\n","Output",1,1,1);
    // PSC0
    PSC0_LPSC_enable(0, LPSC_EDMA_CC0);
    PSC0_LPSC_enable(0, LPSC_EDMA_TC0);
    PSC0_LPSC_enable(0, LPSC_EDMA_TC1);
    PSC0_LPSC_enable(0, LPSC_SPI0);
    PSC0_LPSC_enable(0, LPSC_MMCSD0);
    PSC0_LPSC_enable(0, LPSC_ARM_AINTC);
    PSC0_LPSC_enable(0, LPSC_ARM_RAMROM);
    PSC0_LPSC_enable(0, LPSC_UART0);
    PSC0_LPSC_enable(0, LPSC_SCR0);
    PSC0_LPSC_enable(0, LPSC_SCR1);
    PSC0_LPSC_enable(0, LPSC_SCR2);

    // PSC1
    PSC1_LPSC_enable(0, LPSC_EDMA_CC1);
    PSC1_LPSC_enable(0, LPSC_USB20);
    PSC1_LPSC_enable(0, LPSC_USB11);
    CFGCHIP2 = 0x09F2;  // Enable USB clock, PHY_PLLON, glue logic mux(USB2 ref clk input)
    PSC1_LPSC_enable(0, LPSC_GPIO);
    PSC1_LPSC_enable(0, LPSC_UHPI);
    PSC1_LPSC_enable(0, LPSC_EMAC);
    PSC1_LPSC_enable(0, LPSC_DDR);
    PSC1_LPSC_enable(0, LPSC_MCASP0);
    PSC1_LPSC_force(LPSC_SATA); // Must use force to enable SATA
    PSC1_LPSC_enable(0, LPSC_SATA);
    PSC1_LPSC_enable(0, LPSC_SPI1);
    PSC1_LPSC_enable(0, LPSC_I2C1);
    PSC1_LPSC_enable(0, LPSC_UART1);
    PSC1_LPSC_enable(0, LPSC_UART2);
    PSC1_LPSC_enable(0, LPSC_MCBSP0);
    PSC1_LPSC_enable(0, LPSC_MCBSP1);
    PSC1_LPSC_enable(0, LPSC_EPWM);
    PSC1_LPSC_enable(0, LPSC_MMCSD1);
    PSC1_LPSC_enable(0, LPSC_ECAP);
    PSC1_LPSC_enable(0, LPSC_EDMA_TC2);
    PSC1_LPSC_enable(0, LPSC_SCR_F0);
    PSC1_LPSC_enable(0, LPSC_SCR_F1);
    PSC1_LPSC_enable(0, LPSC_SCR_F2);
    PSC1_LPSC_enable(0, LPSC_SCR_F6);
    PSC1_LPSC_enable(0, LPSC_SCR_F7);
    PSC1_LPSC_enable(0, LPSC_SCR_F8);
    PSC1_LPSC_enable(0, LPSC_BR_F7);
    PSC1_LPSC_enable(0, LPSC_SHARED_RAM);

    GEL_TextOut("\tPSC Enable Complete.\n","Output",1,1,1);
    GEL_TextOut("\t---------------------------------------------\n","Output",1,1,1);
}

menuitem "Full EVM"

hotmenu PSC_All_On_Full_EVM() {
    // PSC0
//    PSC0_LPSC_enable(0, LPSC_EDMA_CC0);
    PSC0_LPSC_enable(0, LPSC_EDMA_TC0);
    PSC0_LPSC_enable(0, LPSC_EDMA_TC1);
    PSC0_LPSC_enable(0, LPSC_EMIFA);
    PSC0_LPSC_enable(0, LPSC_SPI0);
    PSC0_LPSC_enable(0, LPSC_MMCSD0);
    PSC0_LPSC_enable(0, LPSC_ARM_AINTC);
    PSC0_LPSC_enable(0, LPSC_ARM_RAMROM);
    PSC0_LPSC_enable(0, LPSC_UART0);
    PSC0_LPSC_enable(0, LPSC_SCR0);
    PSC0_LPSC_enable(0, LPSC_SCR1);
    PSC0_LPSC_enable(0, LPSC_SCR2);

    // PSC1
//    PSC1_LPSC_enable(0, LPSC_EDMA_CC1);
    PSC1_LPSC_enable(0, LPSC_USB20);
    PSC1_LPSC_enable(0, LPSC_USB11);
    CFGCHIP2 = 0x09F2;  //Enable USB clock, PHY_PLLON, glue logic mux(USB2 ref clk input)
    PSC1_LPSC_enable(0, LPSC_GPIO);
    PSC1_LPSC_enable(0, LPSC_UHPI);
    PSC1_LPSC_enable(0, LPSC_EMAC);
    PSC1_LPSC_enable(0, LPSC_MCASP0);
    PSC1_LPSC_force(LPSC_SATA);
    PSC1_LPSC_enable(0, LPSC_SATA);
    PSC1_LPSC_enable(0, LPSC_VPIF);
    PSC1_LPSC_enable(0, LPSC_SPI1);
    PSC1_LPSC_enable(0, LPSC_I2C1);
    PSC1_LPSC_enable(0, LPSC_UART1);
    PSC1_LPSC_enable(0, LPSC_UART2);
//    PSC1_LPSC_enable(0, LPSC_MCBSP0);
//    PSC1_LPSC_enable(0, LPSC_MCBSP1);
    PSC1_LPSC_enable(0, LPSC_LCDC);
    PSC1_LPSC_enable(0, LPSC_EPWM);
//    PSC1_LPSC_enable(0, LPSC_MMCSD1);
//    PSC1_LPSC_enable(0, LPSC_UPP);
    PSC1_LPSC_enable(0, LPSC_ECAP);
    PSC1_LPSC_enable(0, LPSC_EDMA_TC2);
    PSC1_LPSC_enable(0, LPSC_SCR_F0);
    PSC1_LPSC_enable(0, LPSC_SCR_F1);
    PSC1_LPSC_enable(0, LPSC_SCR_F2);
//    PSC1_LPSC_enable(0, LPSC_SCR_F6);
//    PSC1_LPSC_enable(0, LPSC_SCR_F7);
//    PSC1_LPSC_enable(0, LPSC_SCR_F8);
//    PSC1_LPSC_enable(0, LPSC_BR_F7);
    PSC1_LPSC_enable(0, LPSC_SHARED_RAM);

    GEL_TextOut("\tPSC Enable Complete.\n","Output",1,1,1);
    GEL_TextOut("\t---------------------------------------------\n","Output",1,1,1);
}

hotmenu EMIFA_NAND_PINMUX() {
    PSC0_LPSC_enable(0, LPSC_EMIFA);
    PINMUX7        = (PINMUX7 & ~0x00FF0FF0) | 0x00110110;
    PINMUX9        = 0x11111111;
    PINMUX12       = (PINMUX12 & ~0x0FF00000) | 0x01100000;
    EMIFA_ACFG2  &= ~0x1; // 8-bit
    EMIFA_NANDFCR = (EMIFA_NANDFCR & ~0x30) | 0x12;

    // Set OE Low
    PINMUX6         = (PINMUX6 & ~0x000000F0) | 0x00000080;
    GPIO_BANK23_DIR = (GPIO_BANK23_DIR & ~(1 << 6));
    GPIO_BANK23_CLR = (1 << 6);

    GEL_TextOut("\tEMIFA Pins Configured for NAND.\n","Output",1,1,1);
    GEL_TextOut("\t---------------------------------------------\n","Output",1,1,1);
}

hotmenu EMIFA_NOR_PINMUX() {
    PSC0_LPSC_enable(0, LPSC_EMIFA);
    PINMUX5       = (PINMUX5 & ~0xFF000000) | 0x11000000;
    PINMUX6       = (PINMUX6 & ~0x0F00000F) | 0x01000001;
    PINMUX7       = (PINMUX7 & ~0x00FF000F) | 0x00110001;
    PINMUX8       = 0x11111111;
    PINMUX9       = 0x11111111;
    PINMUX10      = 0x11111111;
    PINMUX11      = 0x11111111;
    PINMUX12      = 0x11111111;
    EMIFA_ACFG2 |= 0x1; // 16-bit

    GEL_TextOut("\tEMIFA Pins Configured for NOR.\n","Output",1,1,1);
    GEL_TextOut("\t---------------------------------------------\n","Output",1,1,1);
}

hotmenu SPI1_PINMUX() {
    PSC1_LPSC_enable(0, LPSC_SPI1);
    PINMUX5 = (PINMUX5 & ~0x00FF0FF0) | 0x00110110;

    GEL_TextOut("\tSPI1 Pins Configured.\n","Output",1,1,1);
    GEL_TextOut("\t---------------------------------------------\n","Output",1,1,1);
}

/**************************************************************************************************************************************************
   Device_PLL0 init:

   CLKMODE -  0---->On Chip Oscilator  1---->External Oscilator
   PLL0_SYSCLK1 - Not used on Freon subchip, fixed divider (/1) - allow to change div1
   PLL0_SYSCLK2 - Used on Freon subchip, but it has a fixed divider ratio to SYSCLK1(/2) - should be used for sc ASYNC3 domain
                  to simplify clock management for peripherals during the ROM boot loader CFGCHIP3[ASYNC3_CLKSRC] - configure with div1
   PLL0_SYSCLK3 - Variable Divider, not used on Freon subchip, but ASYNC1 (EMIFA) on matrix - treat same as in Primus (configure)
   PLL0_SYSCLK4 - Used on Freon subchip, but it has a fixed ratio to div1 (/4) - configure with div1
   PLL0_SYSCLK5 - Variable divider, not used on Freon subchip - do nothing
   PLL0_SYSCLK6 - Not used on Freon subchip, fixed ratio to div1 (/1) - configure with div1
   PLL0_SYSCLK7 - Variable divider, is used on Freon subchip (Test, RMII, possibly USB 1.1) - treat the same as on Primus (configure)
   PLL0_SYSCLK8 - Variable divider, not used on Freon subchip - treat same as in Primus (do nothing)
   PLL0_SYSCLK9 - Variable divider, used on Freon subchip (test) - treat same as in Primus (do nothing)
   DIV4p5CLOCK  - Not used on Freon, can be used in in EMIFA on matrix - treat same as in Primus - configure in EMIF setups, not here
******************************************************************************************************************************************************/
device_PLL0(unsigned int CLKMODE, unsigned int PLLM, unsigned int POSTDIV,unsigned int PLLDIV1, unsigned int PLLDIV2, unsigned int PLLDIV3, unsigned int PLLDIV7 ) {

   unsigned int i=0;

   /* Clear PLL lock bit */
   CFGCHIP0 &= ~(0x00000010);

   /* Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled through MMR */
   PLL0_PLLCTL &= ~(0x00000020);

   /* PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Freon */
   PLL0_PLLCTL &= ~(0x00000200);

   /* Set PLLEN=0 to put in bypass mode*/
   PLL0_PLLCTL &= ~(0x00000001);

   /*wait for 4 cycles to allow PLLEN mux switches properly to bypass clock*/
   for(i=0; i<PLLEN_MUX_SWITCH; i++) {;}

   /* Select the Clock Mode bit 8 as External Clock or On Chip Oscilator*/
   PLL0_PLLCTL &= 0xFFFFFEFF;
   PLL0_PLLCTL |= (CLKMODE << 8);

   /*Clear PLLRST bit to reset the PLL */
   PLL0_PLLCTL &= ~(0x00000008);

   /* Disable the PLL output*/
   PLL0_PLLCTL |= (0x00000010);

   /* PLL initialization sequence
   Power up the PLL by setting PWRDN bit set to 0 */
   PLL0_PLLCTL &= ~(0x00000002);

   /* Enable the PLL output*/
   PLL0_PLLCTL &= ~(0x00000010);

   /*PLL stabilisation time- take out this step , not required here when PLL in bypassmode*/
   for(i=0; i<PLL_STABILIZATION_TIME; i++) {;}

   /*Program the required multiplier value in PLLM*/
   PLL0_PLLM    = PLLM; /* Make PLLMULTIPLEIR as bootpacket*/

   /*If desired to scale all the SYSCLK frequencies of a given PLLC, program the POSTDIV ratio*/
   PLL0_POSTDIV = 0x8000 | POSTDIV; /* Make POSTDIV as bootpacket*/

   /*Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that no GO operation is currently in progress*/
   while(PLL0_PLLSTAT & 0x1==1){}

   /*Program the RATIO field in PLLDIVx with the desired divide factors. In addition, make sure in this step you leave the PLLDIVx.DxEN bits set so clocks are still enabled (default).*/
   PLL0_PLLDIV1 = 0x8000 | PLLDIV1;   /* Make PLLDIV1 as bootpacket, do it for other PLLDIVx to if required*/
   PLL0_PLLDIV2 = 0x8000 | PLLDIV2;
   PLL0_PLLDIV4 = 0x8000 | (((PLLDIV1+1)*4)-1);
   PLL0_PLLDIV6 = 0x8000 | PLLDIV1;
   PLL0_PLLDIV3 = 0x8000 | PLLDIV3;   /* Make PLLDIV3 as bootpacket, do it for other PLLDIVx to if required*/
   PLL0_PLLDIV7 = 0x8000 | PLLDIV7;   /* Make PLLDIV7 as bootpacket, do it for other PLLDIVx to if required*/

   /*Set the GOSET bit in PLLCMD to 1 to initiate a new divider transition.*/
   PLL0_PLLCMD |= 0x1;

   /*Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of phase alignment).*/
   while(PLL0_PLLSTAT & 0x1==1) { }

   /*Wait for PLL to reset properly. See PLL spec for PLL reset time - This step is not required here -step11*/
   for(i=0; i<PLL_RESET_TIME_CNT; i++) {;}   /*128 MXI Cycles*/

   /*Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset*/
   PLL0_PLLCTL |= 0x8;

   /*Wait for PLL to lock. See PLL spec for PLL lock time*/
   for(i=0; i<PLL_LOCK_TIME_CNT; i++) {;} /*Make PLL_LOCK_TIME_CNT as boot Packet*/

   /*Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass mode*/
   PLL0_PLLCTL |=  0x1;

   /* SET PLL lock bit*/
   CFGCHIP0 |= (0x1 << 4) & 0x00000010;
}

/**********************************************************************************
DDR PLL1 init:

***********************************************************************************/

device_PLL1(unsigned int PLLM,unsigned int POSTDIV,unsigned int PLLDIV1, unsigned int PLLDIV2, unsigned int PLLDIV3 ) {

   unsigned int i=0;

   /* Clear PLL lock bit */
   CFGCHIP3 &= ~(0x00000020);

   /* Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled through MMR */
   PLL1_PLLCTL &= ~(0x00000020);

   /* PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Freon */
   PLL1_PLLCTL &= ~(0x00000200);

   /* Set PLLEN=0 to put in bypass mode*/
   PLL1_PLLCTL &= ~(0x00000001);

   /*wait for 4 cycles to allow PLLEN mux switches properly to bypass clock*/
   for(i=0; i<PLLEN_MUX_SWITCH; i++) {;}

   /*Clear PLLRST bit to reset the PLL */
   PLL1_PLLCTL &= ~(0x00000008);

   /* Disable the PLL output*/
   PLL1_PLLCTL |= (0x00000010);

   /* PLL initialization sequence
   Power up the PLL by setting PWRDN bit set to 0 */
   PLL1_PLLCTL &= ~(0x00000002);

   /* Enable the PLL output*/
   PLL1_PLLCTL &= ~(0x00000010);

   /*PLL stabilisation time- take out this step , not required here when PLL in bypassmode*/
   for(i=0; i<PLL_STABILIZATION_TIME; i++) {;}

   /*Program the required multiplier value in PLLM*/
   PLL1_PLLM    = PLLM; /* Make PLLMULTIPLEIR as bootpacket*/

   /*If desired to scale all the SYSCLK frequencies of a given PLLC, program the POSTDIV ratio*/
   PLL1_POSTDIV = 0x8000 | POSTDIV; /* Make POSTDIV as bootpacket*/

   /*Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that no GO operation is currently in progress*/
   while(PLL1_PLLSTAT & 0x1==1){}

   /*Program the RATIO field in PLLDIVx with the desired divide factors. In addition, make sure in this step you leave the PLLDIVx.DxEN bits set so clocks are still enabled (default).*/
   PLL1_PLLDIV1 = 0x8000 | PLLDIV1;   /* Make PLLDIV1 as bootpacket, do it for other PLLDIVx to if required*/
   PLL1_PLLDIV2 = 0x8000 | PLLDIV2;   /* Make PLLDIV2 as bootpacket, do it for other PLLDIVx to if required*/
   PLL1_PLLDIV3 = 0x8000 | PLLDIV3;   /* Make PLLDIV3 as bootpacket, do it for other PLLDIVx to if required*/

   /*Set the GOSET bit in PLLCMD to 1 to initiate a new divider transition.*/
   PLL1_PLLCMD |= 0x1;

   /*Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of phase alignment).*/
   while(PLL1_PLLSTAT & 0x1==1) { }

   /*Wait for PLL to reset properly. See PLL spec for PLL reset time - */
   for(i=0; i<PLL_RESET_TIME_CNT; i++) {;}   /*128 MXI Cycles*/

   /*Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset*/
   PLL1_PLLCTL |= 0x8;

   /*Wait for PLL to lock. See PLL spec for PLL lock time*/
   for(i=0; i<PLL_LOCK_TIME_CNT; i++) {;} /*Make PLL_LOCK_TIME_CNT as boot Packet*/

   /*Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass mode*/
   PLL1_PLLCTL |=  0x1;

   /* SET PLL lock bit*/
   CFGCHIP3 |= (0x1 << 5) & 0x00000020;

}

/**********************************************************************************
Device Kick Unlock:
    Kick0 register + data (unlock)
    Kick1 register + data (unlock)
***********************************************************************************/
DEVICE_kickUnlock() {
   KICK0R = 0x83e70b13;  // Kick0 register + data (unlock)
   KICK1R = 0x95a4f1e0;  // Kick1 register + data (unlock)
 }

/**********************************************************************************
  PSC Common functions :

***********************************************************************************/
/*Force module state without handshaking */
PSC1_LPSC_force(unsigned int LPSC_num) {
    *(unsigned int*) (PSC1_MDCTL+4*LPSC_num) = (*(unsigned int*) (PSC1_MDCTL+4*LPSC_num) | 0x80000000);
}

/*SyncReset Function for PSC1*/
PSC1_LPSC_SyncReset(unsigned int PD, unsigned int LPSC_num) {
    unsigned int j;

    if( (*(unsigned int*)(PSC1_MDSTAT+4 * LPSC_num) & 0x1F) != 0x1 ) {
      *(unsigned int*) (PSC1_MDCTL+4*LPSC_num) = (*(unsigned int*) (PSC1_MDCTL+4*LPSC_num) & 0xFFFFFFE0) | 0x0001;
      PSC1_PTCMD = 0x1<<PD;

      j = 0;
      /*Wait for power state transition to finish*/
      while( (PSC1_PTSTAT & (0x1<<PD) ) !=0) {
        if( j++ > PSC_TIMEOUT ) {
          GEL_TextOut("\tPSC1 Sync Reset Transition Timeout on Domain %d, LPSC %d\n","Output",1,1,1,PD,LPSC_num);
          break;
        }
      }

      j = 0;
      while( (*(unsigned int*)(PSC1_MDSTAT+4 * LPSC_num) & 0x1F) !=0x1) {
        if( j++ > PSC_TIMEOUT ) {
          GEL_TextOut("\tPSC1 Sync Reset Verify Timeout on Domain %d, LPSC %d\n","Output",1,1,1,PD,LPSC_num);
          break;
        }
      }
    }
}

/*Enable Function for PSC1*/
PSC1_LPSC_enable(unsigned int PD, unsigned int LPSC_num) {
    unsigned int j;
   
    if( (*(unsigned int*)(PSC1_MDSTAT+4 * LPSC_num) & 0x1F) != 0x3 ) {
      *(unsigned int*) (PSC1_MDCTL+4*LPSC_num) = (*(unsigned int*) (PSC1_MDCTL+4*LPSC_num) & 0xFFFFFFE0) | 0x0003;
      PSC1_PTCMD = 0x1<<PD;

      j = 0;
      /*Wait for power state transition to finish*/
      while( (PSC1_PTSTAT & (0x1<<PD) ) !=0) {
        if( j++ > PSC_TIMEOUT ) {
          GEL_TextOut("\tPSC1 Enable Transition Timeout on Domain %d, LPSC %d\n","Output",1,1,1,PD,LPSC_num);
          break;
        }
      }

      j = 0;
      while( (*(unsigned int*)(PSC1_MDSTAT+4 * LPSC_num) & 0x1F) !=0x3) {
        if( j++ > PSC_TIMEOUT ) {
          GEL_TextOut("\tPSC1 Enable Verify Timeout on Domain %d, LPSC %d\n","Output",1,1,1,PD,LPSC_num);
          break;
        }
      }
    }
}

/*LPSC Enable Function for ARM or DSP*/
PSC0_LPSC_enableCore(unsigned int PD, unsigned int LPSC_num) {
    unsigned int j;
   
    if( (*(unsigned int*)(PSC0_MDSTAT+4 * LPSC_num) & 0x11F) != 0x103 ) {
      *(unsigned int*) (PSC0_MDCTL+4*LPSC_num) = (*(unsigned int*) (PSC0_MDCTL+4*LPSC_num) & 0xFFFFFEE0) | 0x0103;
      PSC0_PTCMD = 0x1<<PD;

      j = 0;
      /*Wait for power state transition to finish*/
      while( (PSC0_PTSTAT & (0x1<<PD) ) !=0) {
        if( j++ > PSC_TIMEOUT ) {
          GEL_TextOut("\tPSC0 Enable Core Transition Timeout on Domain %d, LPSC %d\n","Output",1,1,1,PD,LPSC_num);
          break;
        }
      }
     
      j = 0;
      while( (*(unsigned int*)(PSC0_MDSTAT+4 * LPSC_num) & 0x11F) !=0x103) {
        if( j++ > PSC_TIMEOUT ) {
          GEL_TextOut("\tPSC0 Enable Core Verify Timeout on Domain %d, LPSC %d\n","Output",1,1,1,PD,LPSC_num);
          break;
        }
      }
    }
}

/*SyncReset Function for PSC0*/
PSC0_LPSC_SyncReset(unsigned int PD, unsigned int LPSC_num) {
    unsigned int j;
   
    if( (*(unsigned int*)(PSC0_MDSTAT+4 * LPSC_num) & 0x1F) != 0x1 ) {
      *(unsigned int*) (PSC0_MDCTL+4*LPSC_num) = (*(unsigned int*) (PSC0_MDCTL+4*LPSC_num) & 0xFFFFFFE0) | 0x0001;
      PSC0_PTCMD = 0x1<<PD;

      j = 0;
      /*Wait for power state transition to finish*/
      while( (PSC0_PTSTAT & (0x1<<PD) ) !=0) {
        if( j++ > PSC_TIMEOUT ) {
          GEL_TextOut("\tPSC0 Sync Reset Transition Timeout on Domain %d, LPSC %d\n","Output",1,1,1,PD,LPSC_num);
          break;
        }
      }

      j = 0;
      while( (*(unsigned int*)(PSC0_MDSTAT+4 * LPSC_num) & 0x1F) !=0x1) {
        if( j++ > PSC_TIMEOUT ) {
          GEL_TextOut("\tPSC0 Sync Reset Verify Timeout on Domain %d, LPSC %d\n","Output",1,1,1,PD,LPSC_num);
          break;
        }
      }
    }
}

/*Enable Function for PSC0*/
PSC0_LPSC_enable(unsigned int PD, unsigned int LPSC_num) {
    unsigned int j;

    if( (*(unsigned int*)(PSC0_MDSTAT+4 * LPSC_num) & 0x1F) != 0x3 ) {
      *(unsigned int*) (PSC0_MDCTL+4*LPSC_num) = (*(unsigned int*) (PSC0_MDCTL+4*LPSC_num) & 0xFFFFFFE0) | 0x0003;
      PSC0_PTCMD = 0x1<<PD;

      j = 0;
      /*Wait for power state transition to finish*/
      while( (PSC0_PTSTAT & (0x1<<PD) ) !=0) {
        if( j++ > PSC_TIMEOUT ) {
          GEL_TextOut("\tPSC0 Enable Transition Timeout on Domain %d, LPSC %d\n","Output",1,1,1,PD,LPSC_num);
          break;
        }
      }

      j = 0;
      while( (*(unsigned int*)(PSC0_MDSTAT+4 * LPSC_num) & 0x1F) !=0x3) {
        if( j++ > PSC_TIMEOUT ) {
          GEL_TextOut("\tPSC0 Enable Verify Timeout on Domain %d, LPSC %d\n","Output",1,1,1,PD,LPSC_num);
          break;
        }
      }
    }
}

/**********************************************************************************
  DDR Configuration routine:
    1. DDR Enable
    2. VTP calibration
    3. Configure DDR
    4. Set to self-refresh, enable mclkstop and DDR Sync Reset
    5. Enable DDR and disable self-refresh

  int freq is MHz

  DDR2 = 0
  MDDR = 1

  A DDR configuration spreadsheet tool is located here:
    http://processors.wiki.ti.com/index.php/Programming_mDDR/DDR2_EMIF_on_OMAP-L1x/C674x

***********************************************************************************/

DEVICE_DDRConfig(unsigned int ddr_type, unsigned int freq)
{
    unsigned int j;
    unsigned int tmp_SDCR;
   
    // Enable the Clock to EMIFDDR SDRAM
    PSC1_LPSC_enable(PD0, LPSC_DDR);

    // Begin VTP Calibration
    VTPIO_CTL &= ~0x00000040;       // Clear POWERDN
    VTPIO_CTL &= ~0x00000080;       // Clear LOCK
    VTPIO_CTL |=  0x00002000;       // Set CLKRZ in case it was cleared before (VTP looks for CLKRZ edge transition)
    VTPIO_CTL &= ~0x00002000;       // Clear CLKRZ (Use read-modify-write to ensure 1 VTP cycle wait for previous instruction)
    VTPIO_CTL |=  0x00002000;       // Set CLKRZ (Use read-modify-write to ensure 1 VTP cycle wait for previous instruction)

    j = 0;
    // Polling READY bit to see when VTP calibration is done
    while((VTPIO_CTL & 0x00008000) == 0) {
      if( j++ > VTP_TIMEOUT ) {
        GEL_TextOut("\tVTP Ready timeout\n","Output",1,1,1);          
        break;
      }
    }

    VTPIO_CTL |= 0x00000080;       // Set LOCK bit for static calibration mode
    VTPIO_CTL |= 0x00000040;       // Set POWERDN bit to power down VTP module
    // End VTP Calibration

    VTPIO_CTL |= 0x00004000;       // Set IOPWRDN to allow powerdown of input receivers when PWRDNEN is set

    // **********************************************************************************************
    // Setting based on the looser of 512Mb mDDR MT46H32M16LFBF-6,
    //                                  1Gb mDDR MT46H64M16LF-6, or
    //                                  1Gb mDDR MT46H64M16LFBF-6 on EVM
    // Config DDR timings
    DRPYC1R     = (0x0               << 8)   |  // Reserved
                  (0x1               << 7)   |  // EXT_STRBEN
                  (0x1               << 6)   |  // PWRDNEN
                  (0x0               << 3)   |  // Reserved
                  (0x4               << 0);     // RL
    // DRPYC1R Value = 0x000000C4

    if( DDR_DEBUG ) {
      // Configure EMIF with max timings for more slack
      // Try this if memory is not stable
      DRPYC1R  |=  0x7; // RL
    }

    EMIFDDR_SDCR |= 0x00800000; // Set BOOTUNLOCK

    // Settings that change depending on DDR2 or MDDR
    if( ddr_type == DDR2 ) {
      tmp_SDCR = (0x0               << 25)  |  // MSDRAMEN
                 (0x1               << 20);    // DDR2EN
      GEL_TextOut("\tUsing DDR2 settings\n","Output",1,1,1);
    }
    else if( ddr_type == MDDR ) {
      tmp_SDCR = (0x1               << 25)  |  // MSDRAMEN
                 (0x0               << 20);    // DDR2EN
      GEL_TextOut("\tUsing mDDR settings\n","Output",1,1,1);
    }
    else {
      tmp_SDCR = (0x1               << 25)  |  // MSDRAMEN
                 (0x0               << 20);    // DDR2EN
      GEL_TextOut("\tUnknown DDR Type!  Using MDDR settings\n","Output",1,1,1);
    }

    EMIFDDR_SDCR = tmp_SDCR                    |  // Settings that change depending on DDR2 or MDDR
                   (EMIFDDR_SDCR & 0xF0000000) |  // Reserved
                   (0x0               << 27)   |  // DDR2TERM1
                   (0x0               << 26)   |  // IBANK_POS
                   (0x0               << 24)   |  // DDRDRIVE1
                   (0x0               << 23)   |  // BOOTUNLOCK
                   (0x0               << 22)   |  // DDR2DDQS
                   (0x0               << 21)   |  // DDR2TERM0
                   (0x0               << 19)   |  // DDRDLL_DIS
                   (0x0               << 18)   |  // DDRDRIVE0
                   (0x1               << 17)   |  // DDREN
                   (0x1               << 16)   |  // SDRAMEN
                   (0x1               << 15)   |  // TIMUNLOCK
                   (0x1               << 14)   |  // NM
                   (0x0               << 12)   |  // Reserved
                   (0x3               << 9)    |  // CL
                   (0x0               << 7)    |  // Reserved
                   (0x2               << 4)    |  // IBANK
                   (0x0               << 3)    |  // Reserved
                   (0x2               << 0);      // PAGESIZE
    // mDDR SDCR Value = 0x02034622

    if( ddr_type == MDDR ) {
      EMIFDDR_SDCR2   = 0x00000000; // IBANK_POS set to 0 so this register does not apply
    }

    if( DDR_DEBUG ) {
      // Configure EMIF with max timings for more slack
      // Try this if memory is not stable

      EMIFDDR_SDTIMR1 = (0x7F << 25)             |  // tRFC
                        (0x07 << 22)             |  // tRP
                        (0x07 << 19)             |  // tRCD
                        (0x07 << 16)             |  // tWR
                        (0x1F << 11)             |  // tRAS
                        (0x1F << 6)              |  // tRC
                        (0x07 << 3)              |  // tRRD
                        (EMIFDDR_SDTIMR1 & 0x4)  |  // Reserved
                        (0x03 << 0);                // tWTR

      EMIFDDR_SDTIMR2 = (EMIFDDR_SDTIMR2 & 0x80000000)                       |  // Reserved
                        (((unsigned int) ((70000 / 7812.5) - 0.5))  << 27)   |  // tRASMAX
                        (0x3                                        << 25)   |  // tXP
                        (0x0                                        << 23)   |  // tODT (Not supported)
                        (0x7F                                       << 16)   |  // tXSNR
                        (0xFF                                       << 8)    |  // tXSRD
                        (0x07                                       << 5)    |  // tRTP (1 Cycle)
                        (0x1F                                       << 0);      // tCKE

      // SDTIMR1 Value = 0xFFFFFFFB
      // SDTIMR2 Value = 0x467FFFFF

      GEL_TextOut("\tDDR Timings Configured for Debug\n","Output",1,1,1);
    }
    else {
      // Let float -> integer truncate handle minus 1; Safer to round up for timings
      EMIFDDR_SDTIMR1 = (((unsigned int) (110.0 * freq / 1000))  << 25)  |  // tRFC
                        (((unsigned int) ( 18.0 * freq / 1000))  << 22)  |  // tRP
                        (((unsigned int) ( 18.0 * freq / 1000))  << 19)  |  // tRCD
                        (((unsigned int) ( 15.0 * freq / 1000))  << 16)  |  // tWR
                        (((unsigned int) ( 42.0 * freq / 1000))  << 11)  |  // tRAS
                        (((unsigned int) ( 60.0 * freq / 1000))  << 6)   |  // tRC
                        (((unsigned int) ( 12.0 * freq / 1000))  << 3)   |  // tRRD
                        (EMIFDDR_SDTIMR1 & 0x4)                          |  // Reserved
                        ((2 - 1)                                 << 0);     // tWTR

      EMIFDDR_SDTIMR2 = (EMIFDDR_SDTIMR2 & 0x80000000)                    |  // Reserved
                        (((unsigned int) ((70000 / 7812.5) - 1)) << 27)   |  // tRASMAX
                        (0x3                                     << 25)   |  // tXP (Should be 6-1 per MT46H64M16LFBF-6 datasheet, but field only goes up to 0b11)
                        (0x0                                     << 23)   |  // tODT (Not supported)
                        (((unsigned int) (138.0 * freq / 1000))  << 16)   |  // tXSNR (tXSR for mDDR)
                        (((unsigned int) (138.0 * freq / 1000))  << 8)    |  // tXSRD (tXSR for mDDR)
                        ((2 - 1)                                 << 5)    |  // tRTP
                        ((1 - 1)                                 << 0);      // tCKE

      // SDTIMR1 Value @ 150MHz = 0x20923249
      // SDTIMR2 Value @ 150MHz = 0x3E141420
    }
 
    EMIFDDR_SDCR    &= ~0x00008000; // Clear TIMUNLOCK

    // Let float -> integer truncate handle RR round-down; Safer to round down for refresh rate
    EMIFDDR_SDRCR   = (0x1                                  << 31)  |  // LPMODEN (Required for LPSC SyncReset/Enable)
                      (0x1                                  << 30)  |  // MCLKSTOPEN (Required for LPSC SyncReset/Enable)
                      (0x0                                  << 24)  |  // Reserved
                      (0x0                                  << 23)  |  // SR_PD
                      (0x0                                  << 16)  |  // Reserved
                      (((unsigned int) (7.8125 * freq))     << 0);     // RR

    // SyncReset the Clock to EMIFDDR SDRAM
    PSC1_LPSC_SyncReset(PD0, LPSC_DDR);

    // Enable the Clock to EMIFDDR SDRAM
    PSC1_LPSC_enable(PD0, LPSC_DDR);

    // Disable self-refresh
    EMIFDDR_SDRCR &= ~0xC0000000;
    // SDRCR Value @ 150MHz = 0x00000493
   
    // Set PBBPR to a value lower than default to prevent blocking
    EMIFDDR_PBBPR = 0x30;
}