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Original question:

PMP9175: Question for PMP9175 and EMC

PMP9175: adjusting synchronous FET circuit to avoid ripple

Taku Kato
Prodigy 90 points
Part Number: PMP9175

Dear engineer

Hi, I'm Taku.


I designed the power supply circuit of PoE with reference to the circuit diagram of PMP9175.

#Almost imitated the design of PMP9175

Now i check my prototype,

then a very large ripple voltage is applied between B and E of the transistor corresponding to Q6 in PMP9175.

TI engineer says 

"R17, R18 and C16 help to control the turn on and turn off time of the synchronous FET.  The sync FET must have very fast turn off to minimize the time that both the primary FET and sync FET are on to limit any shoot-through current.  Yes, the EMI can get worse if the shoot-through is too large.  The key is to use a sync FET with very fast turn-off time.  The capacitance of a diode rectifier causes similar turn-off votlage spikes, resulting in similar EMI."

in below.
https://e2e.ti.com/support/tools/simulation-hardware-system-design-tools-group/sim-hw-system-design/f/simulation-hardware-system-design-tools-forum/665046/pmp9175-question-for-pmp9175-and-emc?tisearch=e2e-sitesearch&keymatch=PMP9175%20R18#

That means that I should change constants of R17,18/ C16 a bit while checking the waveform to prevent ripple?

If so, please tell me what i should be careful about when adjusting.

  • 0
    TI__Intellectual 2530 points

    Taku,

    If you used the same FETs and transformer R17, R18, C16 should not require adjusting.  If they are different from PMP9175, then some adjustment might be necessary.  The critical transition is the turn-off of Q7.  This can require adjusting C16 up or down a few standard values.  You need to look at the voltage across Q7 (or Q7 source to GND) at turn-off and adjust C16 to minimize the voltage spike.  You need to do this measurement at no load and maximum load.  Also look at the input current while making these adjustments to make sure the efficiency is not negatively affected.  I am not sure what you mean by large ripple.  This is the gate drive so there is going to be some square wave voltage across these points at the switching frequency.  Sometimes increasing the value of R24 to slow down the turn-on of Q8 helps.  I have used up to 100 ohms on some designs, but keep it as small as possible.  Again, make sure you don't slow down the turn-on of Q8 too much so that you degrade the efficiency.

    Thanks,

    David

  • 0
    Prodigy 90 points

    Dear David,

    Thank you for your replay.

    I changed flyback transformer and FETs.

    Learge ripple means that there are learge spike between B-E of Q6 when Q7/Q8 are switched. it was over the rating.

    I found it would be better if i make C16 a little bigger(510pF) or R18 a little bigger(5.1k orm).

    Of course i will check turn off of Q7.

    Is It Okey to adjust R18 in the same way as you said for C16?

    Thanks,

    Taku