I'd like to design an DC/DC Vin=20-28V, Vout=55V(For PoE application), Pin=60W at 20Vin, 100W at 28Vin isolated converter.
After check the reference design experiment eff around 90%. But, our target Eff is 92%.
1. Do you have any suggestion to improve the efficiency? Any recommend for pri-MOSFET, Secondary-diode or XTMR construction design
2. How about use 2 x 60W flyback in parallel with power limit design? is this idea can achieve higher eff.?
3. Or need to change another topology like ACF?
Thank you very much.