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TIDM-02002: CLLLC

huang bin
Prodigy 70 points

Part Number: TIDM-02002
Other Parts Discussed in Thread: TMS320F28377D,

dear TI,

      I designed a CLLLC project with TMS320F28377D MCU refer to TIDM-02002 reference design. 

      PWM3 PWM4 PWM5 PWM6 drive CLLLC, which works on 190kHz without high resolution PWM.

      As active synchronous rectification scheme is used , I config Primary tank to trip secondary LEGs under the condition of primary to secondary power flow, but it didn’t work. (secondary tank trips secondary LEGs on the reference design TIDM-02002.)

     But when I config the primary tank to trip primary LEGs under the condition of secondary to primary power flow , it works properly.

 

void CLLLC_HAL_setupSynchronousRectificationAction(uint16_t powerFlow)

{

    if(powerFlow == CLLLC_POWER_FLOW_PRIM_SEC)

    {

        //

       //Enable CMPSS

       //

       CMPSS_enableModule(CLLLC_IPRIM_TANK_CMPSS_BASE);

 

       //

       //Use VDDA as the reference for comparator DACs

       //

       CMPSS_configDAC(CLLLC_IPRIM_TANK_CMPSS_BASE,

                      CMPSS_DACVAL_SYSCLK | CMPSS_DACREF_VDDA

                      | CMPSS_DACSRC_SHDW);

 

       //

       // set DAC H and L values

       //

       CMPSS_setDACValueHigh(CLLLC_IPRIM_TANK_CMPSS_BASE,

                             CLLLC_IPRIM_TANK_DACHVAL);

//        CMPSS_setDACValueLow(CLLLC_IPRIM_TANK_CMPSS_BASE,

//                             CLLLC_IPRIM_TANK_DACLVAL);

 

       //

       // CMPH comparison is inverted because we want to trip for xA

       // when this signal goes below zero, as the pin is connected to + sign

       // the output needs to be inverted to be the right logical level

       //

       CMPSS_configHighComparator(CLLLC_IPRIM_TANK_CMPSS_BASE,

                                  CMPSS_INSRC_DAC | CMPSS_INV_INVERTED);

 

       //

       // CMPL is not inverted because we want to trip when the

       // signal goes above zero, CMPSS pin is connected to + sign of

       // the comparator, hence no sign inversion required

       //

//        CMPSS_configLowComparator(CLLLC_IPRIM_TANK_CMPSS_BASE,

//                                  CMPSS_INSRC_DAC );

 

 

       CMPSS_configLatchOnPWMSYNC(CLLLC_IPRIM_TANK_CMPSS_BASE, TRUE, TRUE);

 

       EALLOW;

//        HWREGH(CLLLC_IPRIM_TANK_CMPSS_BASE + CMPSS_O_COMPDACCTL) |= 0x1E;

       HWREGH(CLLLC_IPRIM_TANK_CMPSS_BASE + CMPSS_O_COMPDACCTL) |= 0x0E;

       EDIS;

 

       //

       // configure the filter to the lowest setting

       //

       CMPSS_configFilterHigh(CLLLC_IPRIM_TANK_CMPSS_BASE, 0, 1, 1);

//        CMPSS_configFilterLow(CLLLC_IPRIM_TANK_CMPSS_BASE, 0, 1, 1);

 

       //

       //Reset filter logic & start filtering

       //

       CMPSS_initFilterHigh(CLLLC_IPRIM_TANK_CMPSS_BASE);

//        CMPSS_initFilterLow(CLLLC_IPRIM_TANK_CMPSS_BASE);

 

 

       CMPSS_configOutputsHigh(CLLLC_IPRIM_TANK_CMPSS_BASE,

                               CMPSS_TRIP_LATCH | CMPSS_TRIPOUT_LATCH);

//        CMPSS_configOutputsLow(CLLLC_IPRIM_TANK_CMPSS_BASE,

//                               CMPSS_TRIP_LATCH | CMPSS_TRIPOUT_LATCH);

 

       //

       //Comparator hysteresis control , set to 2x typical value

       //

       CMPSS_setHysteresis(CLLLC_IPRIM_TANK_CMPSS_BASE, 2);

 

       //

       // Clear the latched comparator events

       //

       CMPSS_clearFilterLatchHigh(CLLLC_IPRIM_TANK_CMPSS_BASE);

//        CMPSS_clearFilterLatchLow(CLLLC_IPRIM_TANK_CMPSS_BASE);

 

       XBAR_setEPWMMuxConfig(XBAR_TRIP5,

                             CLLLC_IPRIM_TANK_H_PWM_XBAR_MUX_VAL);

       XBAR_enableEPWMMux(XBAR_TRIP5,

                          CLLLC_IPRIM_TANK_H_XBAR_MUX);

 

//        XBAR_setEPWMMuxConfig(XBAR_TRIP7,

//                              CLLLC_IPRIM_TANK_L_PWM_XBAR_MUX_VAL);

//        XBAR_enableEPWMMux(XBAR_TRIP7,

//                           CLLLC_IPRIM_TANK_L_XBAR_MUX);

 

       XBAR_clearInputFlag(CLLLC_IPRIM_TANK_H_CMPSS_XBAR_FLAG);

//        XBAR_clearInputFlag(CLLLC_IPRIM_TANK_L_CMPSS_XBAR_FLAG);

 

       //

       // configure EPWM to issue blanking pulse

       //

 

       EPWM_setDigitalCompareBlankingEvent(CLLLC_SEC_LEG1_PWM_BASE,

                                       EPWM_DC_WINDOW_START_TBCTR_ZERO_PERIOD);

 

       EPWM_setDigitalCompareWindowOffset(CLLLC_SEC_LEG1_PWM_BASE, 0);

 

       EPWM_setDigitalCompareWindowLength(CLLLC_SEC_LEG1_PWM_BASE, 25);

 

       EPWM_enableDigitalCompareBlankingWindow(CLLLC_SEC_LEG1_PWM_BASE);

 

       //

       // Now also program the behavior of the PWM to accept

       // the TRIP5 and 7 that are generated by the CMPSS

       // Qualify TRIP5 as DCAL event

       // Qualify TRIP7 as DCBL event

       //

 

       EPWM_selectDigitalCompareTripInput(CLLLC_SEC_LEG1_PWM_BASE,

                                          EPWM_DC_TRIP_TRIPIN5,

                                          EPWM_DC_TYPE_DCAL);

 

//        EPWM_selectDigitalCompareTripInput(CLLLC_PRIM_LEG1_PWM_BASE,

//                                           EPWM_DC_TRIP_TRIPIN7,

//                                           EPWM_DC_TYPE_DCBL);

 

//        EPWM_selectDigitalCompareTripInput(CLLLC_PRIM_LEG2_PWM_BASE,

//                                           EPWM_DC_TRIP_TRIPIN7,

//                                           EPWM_DC_TYPE_DCAL);

 

//        EPWM_selectDigitalCompareTripInput(CLLLC_PRIM_LEG2_PWM_BASE,

//                                           EPWM_DC_TRIP_TRIPIN5,

//                                           EPWM_DC_TYPE_DCBL);

       EPWM_selectDigitalCompareTripInput(CLLLC_SEC_LEG2_PWM_BASE,

                                          EPWM_DC_TRIP_TRIPIN5,

                                          EPWM_DC_TYPE_DCAL);

 

       //

       // Qualify DCAEVT2 to be when DCAL is high

       // Qualify DCBEVT2 to be when DCBL is high

       //

       EPWM_setTripZoneDigitalCompareEventCondition(CLLLC_SEC_LEG1_PWM_BASE,

                                         EPWM_TZ_DC_OUTPUT_A2,

                                         EPWM_TZ_EVENT_DCXL_HIGH);

 

//        EPWM_setTripZoneDigitalCompareEventCondition(CLLLC_PRIM_LEG1_PWM_BASE,

//                                          EPWM_TZ_DC_OUTPUT_B2,

//                                          EPWM_TZ_EVENT_DCXL_HIGH);

 

       EPWM_setTripZoneDigitalCompareEventCondition(CLLLC_SEC_LEG2_PWM_BASE,

                                         EPWM_TZ_DC_OUTPUT_A2,

                                         EPWM_TZ_EVENT_DCXL_HIGH);

 

//        EPWM_setTripZoneDigitalCompareEventCondition(CLLLC_PRIM_LEG2_PWM_BASE,

//                                          EPWM_TZ_DC_OUTPUT_B2,

//                                          EPWM_TZ_EVENT_DCXL_HIGH);

 

 

       //

       // sets the ETZE bit to 1, to enable advanced actions on the PWM

       //

       EPWM_enableTripZoneAdvAction(CLLLC_SEC_LEG1_PWM_BASE);

       EPWM_enableTripZoneAdvAction(CLLLC_SEC_LEG2_PWM_BASE);

 

       //

       // first set all the TZCTLDCX registers to do nothing

       //

       EALLOW;

       HWREGH(CLLLC_SEC_LEG1_PWM_BASE + EPWM_O_TZCTLDCA) = 0xFFFF;

//        HWREGH(CLLLC_PRIM_LEG1_PWM_BASE + EPWM_O_TZCTLDCB) = 0xFFFF;

       HWREGH(CLLLC_SEC_LEG2_PWM_BASE + EPWM_O_TZCTLDCA) = 0xFFFF;

//        HWREGH(CLLLC_PRIM_LEG2_PWM_BASE + EPWM_O_TZCTLDCB) = 0xFFFF;

       EDIS;

 

       //

       // now describe the behavior in case when DCAEVT2 and

       //

       EPWM_setTripZoneAdvDigitalCompareActionB(CLLLC_SEC_LEG1_PWM_BASE,

                                       EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_D,

                                       EPWM_TZ_ADV_ACTION_LOW);

 

       EPWM_setTripZoneAdvDigitalCompareActionA(CLLLC_SEC_LEG1_PWM_BASE,

                                       EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_U,

                                       EPWM_TZ_ADV_ACTION_LOW);

 

       EPWM_setTripZoneAdvDigitalCompareActionB(CLLLC_SEC_LEG2_PWM_BASE,

                                       EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_U,

                                       EPWM_TZ_ADV_ACTION_LOW);

 

       EPWM_setTripZoneAdvDigitalCompareActionA(CLLLC_SEC_LEG2_PWM_BASE,

                                       EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_D,

                                       EPWM_TZ_ADV_ACTION_LOW);

 

 

       //

       //    clear the cycle by cycle trip on zero and period

       //

       EPWM_selectCycleByCycleTripZoneClearEvent(CLLLC_SEC_LEG1_PWM_BASE,

                                   EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO_PERIOD);

       EPWM_selectCycleByCycleTripZoneClearEvent(CLLLC_SEC_LEG2_PWM_BASE,

                                   EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO_PERIOD);

 

    }

    else if(powerFlow == CLLLC_POWER_FLOW_SEC_PRIM)

    {

        //

        //Enable CMPSS

        //

        CMPSS_enableModule(CLLLC_IPRIM_TANK_CMPSS_BASE);

 

        //

        //Use VDDA as the reference for comparator DACs

        //

        CMPSS_configDAC(CLLLC_IPRIM_TANK_CMPSS_BASE,

                       CMPSS_DACVAL_SYSCLK | CMPSS_DACREF_VDDA

                       | CMPSS_DACSRC_SHDW);

 

        //

        // set DAC H and L values

        //

        CMPSS_setDACValueHigh(CLLLC_IPRIM_TANK_CMPSS_BASE,

                              CLLLC_IPRIM_TANK_DACHVAL);

//        CMPSS_setDACValueLow(CLLLC_IPRIM_TANK_CMPSS_BASE,

//                             CLLLC_IPRIM_TANK_DACLVAL);

 

        //

        // CMPH comparison is inverted because we want to trip for xA

        // when this signal goes below zero, as the pin is connected to + sign

        // the output needs to be inverted to be the right logical level

        //

        CMPSS_configHighComparator(CLLLC_IPRIM_TANK_CMPSS_BASE,

                                   CMPSS_INSRC_DAC | CMPSS_INV_INVERTED);

 

        //

        // CMPL is not inverted because we want to trip when the

        // signal goes above zero, CMPSS pin is connected to + sign of

        // the comparator, hence no sign inversion required

        //

//        CMPSS_configLowComparator(CLLLC_IPRIM_TANK_CMPSS_BASE,

//                                  CMPSS_INSRC_DAC );

 

 

        CMPSS_configLatchOnPWMSYNC(CLLLC_IPRIM_TANK_CMPSS_BASE, TRUE, TRUE);

 

        EALLOW;

//        HWREGH(CLLLC_IPRIM_TANK_CMPSS_BASE + CMPSS_O_COMPDACCTL) |= 0x1E;

        HWREGH(CLLLC_IPRIM_TANK_CMPSS_BASE + CMPSS_O_COMPDACCTL) |= 0x0E;

        EDIS;

 

        //

        // configure the filter to the lowest setting

        //

        CMPSS_configFilterHigh(CLLLC_IPRIM_TANK_CMPSS_BASE, 0, 1, 1);

//        CMPSS_configFilterLow(CLLLC_IPRIM_TANK_CMPSS_BASE, 0, 1, 1);

 

        //

        //Reset filter logic & start filtering

        //

        CMPSS_initFilterHigh(CLLLC_IPRIM_TANK_CMPSS_BASE);

//        CMPSS_initFilterLow(CLLLC_IPRIM_TANK_CMPSS_BASE);

 

 

        CMPSS_configOutputsHigh(CLLLC_IPRIM_TANK_CMPSS_BASE,

                                CMPSS_TRIP_LATCH | CMPSS_TRIPOUT_LATCH);

//        CMPSS_configOutputsLow(CLLLC_IPRIM_TANK_CMPSS_BASE,

//                               CMPSS_TRIP_LATCH | CMPSS_TRIPOUT_LATCH);

 

        //

        //Comparator hysteresis control , set to 2x typical value

        //

        CMPSS_setHysteresis(CLLLC_IPRIM_TANK_CMPSS_BASE, 2);

 

        //

        // Clear the latched comparator events

        //

        CMPSS_clearFilterLatchHigh(CLLLC_IPRIM_TANK_CMPSS_BASE);

//        CMPSS_clearFilterLatchLow(CLLLC_IPRIM_TANK_CMPSS_BASE);

 

        XBAR_setEPWMMuxConfig(XBAR_TRIP5,

                              CLLLC_IPRIM_TANK_H_PWM_XBAR_MUX_VAL);

        XBAR_enableEPWMMux(XBAR_TRIP5,

                           CLLLC_IPRIM_TANK_H_XBAR_MUX);

 

//        XBAR_setEPWMMuxConfig(XBAR_TRIP7,

//                              CLLLC_IPRIM_TANK_L_PWM_XBAR_MUX_VAL);

//        XBAR_enableEPWMMux(XBAR_TRIP7,

//                           CLLLC_IPRIM_TANK_L_XBAR_MUX);

 

        XBAR_clearInputFlag(CLLLC_IPRIM_TANK_H_CMPSS_XBAR_FLAG);

//        XBAR_clearInputFlag(CLLLC_IPRIM_TANK_L_CMPSS_XBAR_FLAG);

 

        //

        // configure EPWM to issue blanking pulse

        //

 

        EPWM_setDigitalCompareBlankingEvent(CLLLC_PRIM_LEG1_PWM_BASE,

                                        EPWM_DC_WINDOW_START_TBCTR_ZERO_PERIOD);

 

        EPWM_setDigitalCompareWindowOffset(CLLLC_PRIM_LEG1_PWM_BASE, 0);

 

        EPWM_setDigitalCompareWindowLength(CLLLC_PRIM_LEG1_PWM_BASE, 25);

 

        EPWM_enableDigitalCompareBlankingWindow(CLLLC_PRIM_LEG1_PWM_BASE);

 

        //

        // Now also program the behavior of the PWM to accept

        // the TRIP5 and 7 that are generated by the CMPSS

        // Qualify TRIP5 as DCAL event

        // Qualify TRIP7 as DCBL event

        //

 

        EPWM_selectDigitalCompareTripInput(CLLLC_PRIM_LEG1_PWM_BASE,

                                           EPWM_DC_TRIP_TRIPIN5,

                                           EPWM_DC_TYPE_DCAL);

 

//        EPWM_selectDigitalCompareTripInput(CLLLC_PRIM_LEG1_PWM_BASE,

//                                           EPWM_DC_TRIP_TRIPIN7,

//                                           EPWM_DC_TYPE_DCBL);

 

//        EPWM_selectDigitalCompareTripInput(CLLLC_PRIM_LEG2_PWM_BASE,

//                                           EPWM_DC_TRIP_TRIPIN7,

//                                           EPWM_DC_TYPE_DCAL);

 

//        EPWM_selectDigitalCompareTripInput(CLLLC_PRIM_LEG2_PWM_BASE,

//                                           EPWM_DC_TRIP_TRIPIN5,

//                                           EPWM_DC_TYPE_DCBL);

        EPWM_selectDigitalCompareTripInput(CLLLC_PRIM_LEG2_PWM_BASE,

                                           EPWM_DC_TRIP_TRIPIN5,

                                           EPWM_DC_TYPE_DCAL);

 

        //

        // Qualify DCAEVT2 to be when DCAL is high

        // Qualify DCBEVT2 to be when DCBL is high

        //

        EPWM_setTripZoneDigitalCompareEventCondition(CLLLC_PRIM_LEG1_PWM_BASE,

                                          EPWM_TZ_DC_OUTPUT_A2,

                                          EPWM_TZ_EVENT_DCXL_HIGH);

 

//        EPWM_setTripZoneDigitalCompareEventCondition(CLLLC_PRIM_LEG1_PWM_BASE,

//                                          EPWM_TZ_DC_OUTPUT_B2,

//                                          EPWM_TZ_EVENT_DCXL_HIGH);

 

        EPWM_setTripZoneDigitalCompareEventCondition(CLLLC_PRIM_LEG2_PWM_BASE,

                                          EPWM_TZ_DC_OUTPUT_A2,

                                          EPWM_TZ_EVENT_DCXL_HIGH);

 

//        EPWM_setTripZoneDigitalCompareEventCondition(CLLLC_PRIM_LEG2_PWM_BASE,

//                                          EPWM_TZ_DC_OUTPUT_B2,

//                                          EPWM_TZ_EVENT_DCXL_HIGH);

 

 

        //

        // sets the ETZE bit to 1, to enable advanced actions on the PWM

        //

        EPWM_enableTripZoneAdvAction(CLLLC_PRIM_LEG1_PWM_BASE);

        EPWM_enableTripZoneAdvAction(CLLLC_PRIM_LEG2_PWM_BASE);

 

        //

        // first set all the TZCTLDCX registers to do nothing

        //

        EALLOW;

        HWREGH(CLLLC_PRIM_LEG1_PWM_BASE + EPWM_O_TZCTLDCA) = 0xFFFF;

//        HWREGH(CLLLC_PRIM_LEG1_PWM_BASE + EPWM_O_TZCTLDCB) = 0xFFFF;

        HWREGH(CLLLC_PRIM_LEG2_PWM_BASE + EPWM_O_TZCTLDCA) = 0xFFFF;

//        HWREGH(CLLLC_PRIM_LEG2_PWM_BASE + EPWM_O_TZCTLDCB) = 0xFFFF;

        EDIS;

 

        //

        // now describe the behavior in case when DCAEVT2 and

        //

        EPWM_setTripZoneAdvDigitalCompareActionA(CLLLC_PRIM_LEG1_PWM_BASE,

                                        EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_U,

                                        EPWM_TZ_ADV_ACTION_LOW);

 

        EPWM_setTripZoneAdvDigitalCompareActionB(CLLLC_PRIM_LEG1_PWM_BASE,

                                        EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_D,

                                        EPWM_TZ_ADV_ACTION_LOW);

 

        EPWM_setTripZoneAdvDigitalCompareActionA(CLLLC_PRIM_LEG2_PWM_BASE,

                                        EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_D,

                                        EPWM_TZ_ADV_ACTION_LOW);

 

        EPWM_setTripZoneAdvDigitalCompareActionB(CLLLC_PRIM_LEG2_PWM_BASE,

                                        EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_U,

                                        EPWM_TZ_ADV_ACTION_LOW);

 

        //

        //    clear the cycle by cycle trip on zero and period

        //

        EPWM_selectCycleByCycleTripZoneClearEvent(CLLLC_PRIM_LEG1_PWM_BASE,

                                    EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO_PERIOD);

        EPWM_selectCycleByCycleTripZoneClearEvent(CLLLC_PRIM_LEG2_PWM_BASE,

                                    EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO_PERIOD);

 

 

    }

 

}

  • 0
    TI__Mastermind 42195 points

    This is far too much code to review. Please provide a snippet of the configuration code that you have modified.

    It sounds like you are trying to use the primary side tank to trip the secondary side during reverse conduction, is that correct?

    1. I think it would be good for you to write down the full trip path, something like the following: ADC/CMPSS-> PINx -> CMPSS -> DCCMP tripxyz -> DCxU/DCxB -> PWM5a/b
      1. This will make it very clear where you need to be debugging
    2. Are you sure you are hitting a value that should trip the PWMs? Have you verified this using an oscilloscope?

    Regards,
    Cody  

  • 0 in reply to Cody Watkins
    Prodigy 70 points

         Since the primary tank current is rectified on my project , the only CLLLC_IPRIM_TANK_DACHVAL is used .

         DCAEVT2 is generated , but the PWM5 and PWM6 does not be tripped.

         the code list below.

    void CLLLC_HAL_setupSynchronousRectificationAction(uint16_t powerFlow)
{
    if(powerFlow == CLLLC_POWER_FLOW_PRIM_SEC)
    {
        //
       //Enable CMPSS
       //
       CMPSS_enableModule(CLLLC_IPRIM_TANK_CMPSS_BASE);

       //
       //Use VDDA as the reference for comparator DACs
       //
       CMPSS_configDAC(CLLLC_IPRIM_TANK_CMPSS_BASE,
                      CMPSS_DACVAL_SYSCLK | CMPSS_DACREF_VDDA
                      | CMPSS_DACSRC_SHDW);

       //
       // set DAC H and L values
       // #define CLLLC_IPRIM_TANK_DACHVAL 2000  // 1.46=2000*3/4096
       CMPSS_setDACValueHigh(CLLLC_IPRIM_TANK_CMPSS_BASE,
                             CLLLC_IPRIM_TANK_DACHVAL);
//        CMPSS_setDACValueLow(CLLLC_IPRIM_TANK_CMPSS_BASE,
//                             CLLLC_IPRIM_TANK_DACLVAL);

       //
       // CMPH comparison is inverted because we want to trip for xA
       // when this signal goes below zero, as the pin is connected to + sign
       // the output needs to be inverted to be the right logical level
       //
       CMPSS_configHighComparator(CLLLC_IPRIM_TANK_CMPSS_BASE,
                                  CMPSS_INSRC_DAC | CMPSS_INV_INVERTED);

       //
       // CMPL is not inverted because we want to trip when the
       // signal goes above zero, CMPSS pin is connected to + sign of
       // the comparator, hence no sign inversion required
       //
//        CMPSS_configLowComparator(CLLLC_IPRIM_TANK_CMPSS_BASE,
//                                  CMPSS_INSRC_DAC );

       //
       // configure PRIM PWM LEG1 PWM to issue the blanking signal
       //
//       CMPSS_configBlanking(CLLLC_IPRIM_TANK_CMPSS_BASE,
//                            CLLLC_PRIM_LEG1_PWM_NO);

//       CMPSS_enableBlanking(CLLLC_IPRIM_TANK_CMPSS_BASE);

       CMPSS_configLatchOnPWMSYNC(CLLLC_IPRIM_TANK_CMPSS_BASE, TRUE, TRUE);

       EALLOW;
//        HWREGH(CLLLC_IPRIM_TANK_CMPSS_BASE + CMPSS_O_COMPDACCTL) |= 0x1E;
       HWREGH(CLLLC_IPRIM_TANK_CMPSS_BASE + CMPSS_O_COMPDACCTL) |= 0x0E;
       EDIS;

       //
       // configure the filter to the lowest setting
       //
       CMPSS_configFilterHigh(CLLLC_IPRIM_TANK_CMPSS_BASE, 0, 1, 1);
//        CMPSS_configFilterLow(CLLLC_IPRIM_TANK_CMPSS_BASE, 0, 1, 1);

       //
       //Reset filter logic & start filtering
       //
       CMPSS_initFilterHigh(CLLLC_IPRIM_TANK_CMPSS_BASE);
//        CMPSS_initFilterLow(CLLLC_IPRIM_TANK_CMPSS_BASE);


       CMPSS_configOutputsHigh(CLLLC_IPRIM_TANK_CMPSS_BASE,
                               CMPSS_TRIP_LATCH | CMPSS_TRIPOUT_LATCH);
//        CMPSS_configOutputsLow(CLLLC_IPRIM_TANK_CMPSS_BASE,
//                               CMPSS_TRIP_LATCH | CMPSS_TRIPOUT_LATCH);

       //
       //Comparator hysteresis control , set to 2x typical value
       //
       CMPSS_setHysteresis(CLLLC_IPRIM_TANK_CMPSS_BASE, 2);

       //
       // Clear the latched comparator events
       //
       CMPSS_clearFilterLatchHigh(CLLLC_IPRIM_TANK_CMPSS_BASE);
//        CMPSS_clearFilterLatchLow(CLLLC_IPRIM_TANK_CMPSS_BASE);

       XBAR_setEPWMMuxConfig(XBAR_TRIP5,
                             CLLLC_IPRIM_TANK_H_PWM_XBAR_MUX_VAL);
       XBAR_enableEPWMMux(XBAR_TRIP5,
                          CLLLC_IPRIM_TANK_H_XBAR_MUX);

//        XBAR_setEPWMMuxConfig(XBAR_TRIP7,
//                              CLLLC_IPRIM_TANK_L_PWM_XBAR_MUX_VAL);
//        XBAR_enableEPWMMux(XBAR_TRIP7,
//                           CLLLC_IPRIM_TANK_L_XBAR_MUX);

       XBAR_clearInputFlag(CLLLC_IPRIM_TANK_H_CMPSS_XBAR_FLAG);
//        XBAR_clearInputFlag(CLLLC_IPRIM_TANK_L_CMPSS_XBAR_FLAG);

       //
       // configure EPWM to issue blanking pulse
       //

       EPWM_setDigitalCompareBlankingEvent(CLLLC_SEC_LEG1_PWM_BASE,
                                       EPWM_DC_WINDOW_START_TBCTR_ZERO_PERIOD);

       EPWM_setDigitalCompareWindowOffset(CLLLC_SEC_LEG1_PWM_BASE, 0);

       EPWM_setDigitalCompareWindowLength(CLLLC_SEC_LEG1_PWM_BASE, 25);

       EPWM_enableDigitalCompareBlankingWindow(CLLLC_SEC_LEG1_PWM_BASE);

       //
       // Now also program the behavior of the PWM to accept
       // the TRIP5 and 7 that are generated by the CMPSS
       // Qualify TRIP5 as DCAL event
       // Qualify TRIP7 as DCBL event
       //

       EPWM_selectDigitalCompareTripInput(CLLLC_SEC_LEG1_PWM_BASE,
                                          EPWM_DC_TRIP_TRIPIN5,
                                          EPWM_DC_TYPE_DCAL);

//        EPWM_selectDigitalCompareTripInput(CLLLC_PRIM_LEG1_PWM_BASE,
//                                           EPWM_DC_TRIP_TRIPIN7,
//                                           EPWM_DC_TYPE_DCBL);

//        EPWM_selectDigitalCompareTripInput(CLLLC_PRIM_LEG2_PWM_BASE,
//                                           EPWM_DC_TRIP_TRIPIN7,
//                                           EPWM_DC_TYPE_DCAL);

//        EPWM_selectDigitalCompareTripInput(CLLLC_PRIM_LEG2_PWM_BASE,
//                                           EPWM_DC_TRIP_TRIPIN5,
//                                           EPWM_DC_TYPE_DCBL);
       EPWM_selectDigitalCompareTripInput(CLLLC_SEC_LEG2_PWM_BASE,
                                          EPWM_DC_TRIP_TRIPIN5,
                                          EPWM_DC_TYPE_DCAL);

       //
       // Qualify DCAEVT2 to be when DCAL is high
       // Qualify DCBEVT2 to be when DCBL is high
       //
       EPWM_setTripZoneDigitalCompareEventCondition(CLLLC_SEC_LEG1_PWM_BASE,
                                         EPWM_TZ_DC_OUTPUT_A2,
                                         EPWM_TZ_EVENT_DCXL_HIGH);

//        EPWM_setTripZoneDigitalCompareEventCondition(CLLLC_PRIM_LEG1_PWM_BASE,
//                                          EPWM_TZ_DC_OUTPUT_B2,
//                                          EPWM_TZ_EVENT_DCXL_HIGH);

       EPWM_setTripZoneDigitalCompareEventCondition(CLLLC_SEC_LEG2_PWM_BASE,
                                         EPWM_TZ_DC_OUTPUT_A2,
                                         EPWM_TZ_EVENT_DCXL_HIGH);

//        EPWM_setTripZoneDigitalCompareEventCondition(CLLLC_PRIM_LEG2_PWM_BASE,
//                                          EPWM_TZ_DC_OUTPUT_B2,
//                                          EPWM_TZ_EVENT_DCXL_HIGH);


       //
       // sets the ETZE bit to 1, to enable advanced actions on the PWM
       //
       EPWM_enableTripZoneAdvAction(CLLLC_SEC_LEG1_PWM_BASE);
       EPWM_enableTripZoneAdvAction(CLLLC_SEC_LEG2_PWM_BASE);

       //
       // first set all the TZCTLDCX registers to do nothing
       //
       EALLOW;
       HWREGH(CLLLC_SEC_LEG1_PWM_BASE + EPWM_O_TZCTLDCA) = 0xFFFF;
//        HWREGH(CLLLC_PRIM_LEG1_PWM_BASE + EPWM_O_TZCTLDCB) = 0xFFFF;
       HWREGH(CLLLC_SEC_LEG2_PWM_BASE + EPWM_O_TZCTLDCA) = 0xFFFF;
//        HWREGH(CLLLC_PRIM_LEG2_PWM_BASE + EPWM_O_TZCTLDCB) = 0xFFFF;
       EDIS;

       //
       // now describe the behavior in case when DCAEVT2 and
       //
       EPWM_setTripZoneAdvDigitalCompareActionB(CLLLC_SEC_LEG1_PWM_BASE,
                                       EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_D,
                                       EPWM_TZ_ADV_ACTION_LOW);

       EPWM_setTripZoneAdvDigitalCompareActionA(CLLLC_SEC_LEG1_PWM_BASE,
                                       EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_U,
                                       EPWM_TZ_ADV_ACTION_LOW);

       EPWM_setTripZoneAdvDigitalCompareActionB(CLLLC_SEC_LEG2_PWM_BASE,
                                       EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_U,
                                       EPWM_TZ_ADV_ACTION_LOW);

       EPWM_setTripZoneAdvDigitalCompareActionA(CLLLC_SEC_LEG2_PWM_BASE,
                                       EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_D,
                                       EPWM_TZ_ADV_ACTION_LOW);


       //
       //    clear the cycle by cycle trip on zero and period
       //
       EPWM_selectCycleByCycleTripZoneClearEvent(CLLLC_SEC_LEG1_PWM_BASE,
                                   EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO_PERIOD);
       EPWM_selectCycleByCycleTripZoneClearEvent(CLLLC_SEC_LEG2_PWM_BASE,
                                   EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO_PERIOD);

    }
    else if(powerFlow == CLLLC_POWER_FLOW_SEC_PRIM)
    {
        //
        //Enable CMPSS
        //
        CMPSS_enableModule(CLLLC_IPRIM_TANK_CMPSS_BASE);

        //
        //Use VDDA as the reference for comparator DACs
        //
        CMPSS_configDAC(CLLLC_IPRIM_TANK_CMPSS_BASE,
                       CMPSS_DACVAL_SYSCLK | CMPSS_DACREF_VDDA
                       | CMPSS_DACSRC_SHDW);

        //
        // set DAC H and L values
        //
        CMPSS_setDACValueHigh(CLLLC_IPRIM_TANK_CMPSS_BASE,
                              CLLLC_IPRIM_TANK_DACHVAL);
//        CMPSS_setDACValueLow(CLLLC_IPRIM_TANK_CMPSS_BASE,
//                             CLLLC_IPRIM_TANK_DACLVAL);

        //
        // CMPH comparison is inverted because we want to trip for xA
        // when this signal goes below zero, as the pin is connected to + sign
        // the output needs to be inverted to be the right logical level
        //
        CMPSS_configHighComparator(CLLLC_IPRIM_TANK_CMPSS_BASE,
                                   CMPSS_INSRC_DAC | CMPSS_INV_INVERTED);

        //
        // CMPL is not inverted because we want to trip when the
        // signal goes above zero, CMPSS pin is connected to + sign of
        // the comparator, hence no sign inversion required
        //
//        CMPSS_configLowComparator(CLLLC_IPRIM_TANK_CMPSS_BASE,
//                                  CMPSS_INSRC_DAC );

        //
        // configure PRIM PWM LEG1 PWM to issue the blanking signal
        //
//        CMPSS_configBlanking(CLLLC_IPRIM_TANK_CMPSS_BASE,
//                             CLLLC_PRIM_LEG1_PWM_NO);
//
//        CMPSS_enableBlanking(CLLLC_IPRIM_TANK_CMPSS_BASE);

        CMPSS_configLatchOnPWMSYNC(CLLLC_IPRIM_TANK_CMPSS_BASE, TRUE, TRUE);

        EALLOW;
//        HWREGH(CLLLC_IPRIM_TANK_CMPSS_BASE + CMPSS_O_COMPDACCTL) |= 0x1E;
        HWREGH(CLLLC_IPRIM_TANK_CMPSS_BASE + CMPSS_O_COMPDACCTL) |= 0x0E;
        EDIS;

        //
        // configure the filter to the lowest setting
        //
        CMPSS_configFilterHigh(CLLLC_IPRIM_TANK_CMPSS_BASE, 0, 1, 1);
//        CMPSS_configFilterLow(CLLLC_IPRIM_TANK_CMPSS_BASE, 0, 1, 1);

        //
        //Reset filter logic & start filtering
        //
        CMPSS_initFilterHigh(CLLLC_IPRIM_TANK_CMPSS_BASE);
//        CMPSS_initFilterLow(CLLLC_IPRIM_TANK_CMPSS_BASE);


        CMPSS_configOutputsHigh(CLLLC_IPRIM_TANK_CMPSS_BASE,
                                CMPSS_TRIP_LATCH | CMPSS_TRIPOUT_LATCH);
//        CMPSS_configOutputsLow(CLLLC_IPRIM_TANK_CMPSS_BASE,
//                               CMPSS_TRIP_LATCH | CMPSS_TRIPOUT_LATCH);

        //
        //Comparator hysteresis control , set to 2x typical value
        //
        CMPSS_setHysteresis(CLLLC_IPRIM_TANK_CMPSS_BASE, 2);

        //
        // Clear the latched comparator events
        //
        CMPSS_clearFilterLatchHigh(CLLLC_IPRIM_TANK_CMPSS_BASE);
//        CMPSS_clearFilterLatchLow(CLLLC_IPRIM_TANK_CMPSS_BASE);

        XBAR_setEPWMMuxConfig(XBAR_TRIP5,
                              CLLLC_IPRIM_TANK_H_PWM_XBAR_MUX_VAL);
        XBAR_enableEPWMMux(XBAR_TRIP5,
                           CLLLC_IPRIM_TANK_H_XBAR_MUX);

//        XBAR_setEPWMMuxConfig(XBAR_TRIP7,
//                              CLLLC_IPRIM_TANK_L_PWM_XBAR_MUX_VAL);
//        XBAR_enableEPWMMux(XBAR_TRIP7,
//                           CLLLC_IPRIM_TANK_L_XBAR_MUX);

        XBAR_clearInputFlag(CLLLC_IPRIM_TANK_H_CMPSS_XBAR_FLAG);
//        XBAR_clearInputFlag(CLLLC_IPRIM_TANK_L_CMPSS_XBAR_FLAG);

        //
        // configure EPWM to issue blanking pulse
        //



        EPWM_setDigitalCompareBlankingEvent(CLLLC_PRIM_LEG1_PWM_BASE,
                                        EPWM_DC_WINDOW_START_TBCTR_ZERO_PERIOD);

        EPWM_setDigitalCompareWindowOffset(CLLLC_PRIM_LEG1_PWM_BASE, 0);

        EPWM_setDigitalCompareWindowLength(CLLLC_PRIM_LEG1_PWM_BASE, 25);

        EPWM_enableDigitalCompareBlankingWindow(CLLLC_PRIM_LEG1_PWM_BASE);

        //
        // Now also program the behavior of the PWM to accept
        // the TRIP5 and 7 that are generated by the CMPSS
        // Qualify TRIP5 as DCAL event
        // Qualify TRIP7 as DCBL event
        //

        EPWM_selectDigitalCompareTripInput(CLLLC_PRIM_LEG1_PWM_BASE,
                                           EPWM_DC_TRIP_TRIPIN5,
                                           EPWM_DC_TYPE_DCAL);

//        EPWM_selectDigitalCompareTripInput(CLLLC_PRIM_LEG1_PWM_BASE,
//                                           EPWM_DC_TRIP_TRIPIN7,
//                                           EPWM_DC_TYPE_DCBL);

//        EPWM_selectDigitalCompareTripInput(CLLLC_PRIM_LEG2_PWM_BASE,
//                                           EPWM_DC_TRIP_TRIPIN7,
//                                           EPWM_DC_TYPE_DCAL);

//        EPWM_selectDigitalCompareTripInput(CLLLC_PRIM_LEG2_PWM_BASE,
//                                           EPWM_DC_TRIP_TRIPIN5,
//                                           EPWM_DC_TYPE_DCBL);
        EPWM_selectDigitalCompareTripInput(CLLLC_PRIM_LEG2_PWM_BASE,
                                           EPWM_DC_TRIP_TRIPIN5,
                                           EPWM_DC_TYPE_DCAL);

        //
        // Qualify DCAEVT2 to be when DCAL is high
        // Qualify DCBEVT2 to be when DCBL is high
        //
        EPWM_setTripZoneDigitalCompareEventCondition(CLLLC_PRIM_LEG1_PWM_BASE,
                                          EPWM_TZ_DC_OUTPUT_A2,
                                          EPWM_TZ_EVENT_DCXL_HIGH);

//        EPWM_setTripZoneDigitalCompareEventCondition(CLLLC_PRIM_LEG1_PWM_BASE,
//                                          EPWM_TZ_DC_OUTPUT_B2,
//                                          EPWM_TZ_EVENT_DCXL_HIGH);

        EPWM_setTripZoneDigitalCompareEventCondition(CLLLC_PRIM_LEG2_PWM_BASE,
                                          EPWM_TZ_DC_OUTPUT_A2,
                                          EPWM_TZ_EVENT_DCXL_HIGH);

//        EPWM_setTripZoneDigitalCompareEventCondition(CLLLC_PRIM_LEG2_PWM_BASE,
//                                          EPWM_TZ_DC_OUTPUT_B2,
//                                          EPWM_TZ_EVENT_DCXL_HIGH);


        //
        // sets the ETZE bit to 1, to enable advanced actions on the PWM
        //
        EPWM_enableTripZoneAdvAction(CLLLC_PRIM_LEG1_PWM_BASE);
        EPWM_enableTripZoneAdvAction(CLLLC_PRIM_LEG2_PWM_BASE);

        //
        // first set all the TZCTLDCX registers to do nothing
        //
        EALLOW;
        HWREGH(CLLLC_PRIM_LEG1_PWM_BASE + EPWM_O_TZCTLDCA) = 0xFFFF;
//        HWREGH(CLLLC_PRIM_LEG1_PWM_BASE + EPWM_O_TZCTLDCB) = 0xFFFF;
        HWREGH(CLLLC_PRIM_LEG2_PWM_BASE + EPWM_O_TZCTLDCA) = 0xFFFF;
//        HWREGH(CLLLC_PRIM_LEG2_PWM_BASE + EPWM_O_TZCTLDCB) = 0xFFFF;
        EDIS;

        //
        // now describe the behavior in case when DCAEVT2 and
        //
        EPWM_setTripZoneAdvDigitalCompareActionA(CLLLC_PRIM_LEG1_PWM_BASE,
                                        EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_U,
                                        EPWM_TZ_ADV_ACTION_LOW);

        EPWM_setTripZoneAdvDigitalCompareActionB(CLLLC_PRIM_LEG1_PWM_BASE,
                                        EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_D,
                                        EPWM_TZ_ADV_ACTION_LOW);

        EPWM_setTripZoneAdvDigitalCompareActionA(CLLLC_PRIM_LEG2_PWM_BASE,
                                        EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_D,
                                        EPWM_TZ_ADV_ACTION_LOW);

        EPWM_setTripZoneAdvDigitalCompareActionB(CLLLC_PRIM_LEG2_PWM_BASE,
                                        EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_U,
                                        EPWM_TZ_ADV_ACTION_LOW);

        //
        //    clear the cycle by cycle trip on zero and period
        //
        EPWM_selectCycleByCycleTripZoneClearEvent(CLLLC_PRIM_LEG1_PWM_BASE,
                                    EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO_PERIOD);
        EPWM_selectCycleByCycleTripZoneClearEvent(CLLLC_PRIM_LEG2_PWM_BASE,
                                    EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO_PERIOD);


    }

}

  • 0 in reply to huang bin
    TI__Mastermind 42195 points

    Huang,

    Can you please indicate what part of the trip logic that you think you have configured in the figure below? Are you intending to use the Trip-Zone's CBC or OST trip? Please note that the DCAEVT2 event can trigger a CBC event, or directly trip the PWM. If it directly trips the PWM, there is additional configuration that must be done, and the behavior is not latched in anyway. If the trip input is removed the forcing action will be removed.

    Regards,
    Cody