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VHDL module incorrect behaviour

Hello Experts,

We have created a VHDL module to generate fixed PWM with a 30% duty cycle at 360KHz. (working fine in vivado simulation) But I see that in tina, its generating 50% duty. We tried adjusting dead time to adjust the duty but got the same issue. Please find the attached captures for the same.

I tried posting this issue to design soft website but the website is not responding.

Regards Vishal.

pwm_fixed360khz_gen_800ns.zip