Complex Multiplication in Hardware Accelerator

Hi Atharva,

Complex multiplication is possible using the HWA. Below are the details -

HWA user guide is split into two parts Radar Hardware Accelerator - Part 1 and Radar Hardware Accelerator - Part 2. The part 2 1.1.2 Complex Multiplication has details of how this can be done.

One vector should be loaded to one of the HWA memory banks, M0, ..,M3, the other vector has to be loaded into HWA RAM memory. You can then execute the HWA PARAM set in FFT mode, but with FFT disabled, and with complex multiplication enabled in the preprocessing block.

For Example, if you want to multiply vector x[i] with vector y[i], you load x[i] into let’s say M0 memory bank, vector y[i] to internal RAM, and direct output to memory M1 to get the product z[i]=x[i]*y[i]*1/2^21. You can also do the summation in the output statistics block to get dot product. .

Select the vector multiplication mode, CMULT_MODE=6 or 7

Vector multiplication mode 1: If the register value is CMULT_MODE = 110b, then the complex multiplier functions in vector multiplication mode 1. The purpose of this mode is to enable element-wise multiplication of two complex vectors, as well as dot-product capability (using statistics block to sum the element-wise multiplication output). The samples from the Input Formatter block constitute one of the two vectors, whereas the other vector is taken from a pre-loaded internal RAM inside the core computational unit. (This internal RAM is a RAM that is normally used by the FFT block when performing 1024-point FFT computation). This internal RAM can store 512-complex samples and hence the vector multiplication can support a maximum of 512 elements of multiplication. The Vector multiplication is not a highly parallelized operation, in the sense that only one complex multiplication is done per 200MHz clock cycle.

Vector multiplication mode 2: If the register value is CMULT_MODE = 111b, then the complex multiplier functions in vector multiplication mode 2, which is slightly different from the earlier mode. The only difference in this case is that at the end of every iteration, the addressing of the internal RAM is not reset, so that for the next iteration, the samples from the internal RAM are picked up with an address that continues from where it left off at the end of the previous iteration. This mode can be used when a given set of input samples needs to be element-wise multiplied with multiple vectors. In this case, the input formatter block can be configured to repeat the same set of samples for multiple iterations, and the internal RAM can be loaded with all the vectors, such that for successive iterations, the input samples are multiplied with successive vectors.

The data needs to be in Q20 format with max magnitude of 1

Regards,

Sudharshan K N