TIDA-01573: Split power and gate ground vs. ground

Emir Karamehmedovic

Part Number: TIDA-01573
Other Parts Discussed in Thread: LMG1020,

Hi! I would like to know the difference, and in which case it is better to have power ground (PGND) loop and gate ground (GND) loop separated as in TIDA-01573 where the grounds only "touch" in the GaN FET. In another reference designs by e.g. EPC using EPC2001/EPC2212 GaN FET driven by the same LMG1020, the ground is common and in the GaN FET datasheets it says "Substrate pin should be connected to Source", that is, the ground is the same for all. Does the desired pulse duration or peak current matter here?

over 2 years ago

0 Sasikala Thangam over 2 years ago

TI__Expert 6940 points

Hi Emir,

Our TI Expert is out of office today. He will get back to you soon with his response.

Thanks

Sasi

0 Ethan Galloway over 2 years ago

TI__Mastermind 20980 points

Hi Emir,

The most important thing is to minimize inductance and resistance between the GaN FET and the gate driver. To that end, the gate driver should be placed as close as possible to the GaN FET to prevent ringing.

Also, the TIDA-01573 was designed to deliver a 60 A pulse for 1 ns so ground lift was major design consideration in the PCB. EPC might not be minimizing ground lift as much because it may not be required as much for the circuit. I have not seen the EPC circuit though. Can you link me to the EPC reference design you are referring to?

Best Regards,
Ethan Galloway

0 Emir Karamehmedovic over 2 years ago in reply to Ethan Galloway

Prodigy 100 points

Thanks Ethan!

The EPC design is here

https://epc-co.com/epc/Portals/0/epc/documents/guides/EPC9126xx_qsg.pdf

There is just ground, no PGND. You can see their gerbers and design here

https://epc-co.com/epc/products/demo-boards/epc9126

On the top layer one can see that all source terminals and the substrate pin of GaN are on the one GND.

+1 Emir Karamehmedovic over 2 years ago in reply to Ethan Galloway

Prodigy 100 points

And just to make it clear, I need a few tens of mA current pulse, not approaching 1A at all, and definitely not 60A. I just need as short pulse as possible without afterpulsing.

0 Ethan Galloway over 2 years ago in reply to Emir Karamehmedovic

TI__Mastermind 20980 points

Hi Emir,

With only a 100 mA pulse, I don't think you'll need to worry about ground lift. I think you should keep the grounds together and aim for the shortest possible connection from the gate driver to the FET.

Either the EPC reference board or the TI reference board would make good examples. The datasheet for the LMG1020 also has layout guidelines. Please let me know if you have any more questions or need more information.

Best Regards,
Ethan Galloway

Because of the holidays, TI E2E™ design support forum responses will be delayed from Dec. 25 through Jan. 2. Thank you for your patience.

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TIDA-01573: Split power and gate ground vs. ground