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Original question:

TIDA-00917: IGBT Gate driver - CM choke sizing and current rating

TIDA-00917: TIDA-00917

Vijaymahantesh Surkod
Intellectual 301 points
Part Number: TIDA-00917


The Texas instruments gate drive reference design (TIDA-00917, https://e2e.ti.com/support/tools/simulation-hardware-system-design-tools-group/sim-hw-system-design/f/simulation-hardware-system-design-tools-forum/1061902/tida-00917-igbt-gate-driver---cm-choke-sizing-and-current-rating ) says that we have to use common mode choke in the gate drive circuit in order to share the dynamic current as shown in the Fig 1.

                                        Fig.1 

1) How does a common mode choke help in doing so? Because if I assume a current flowing through the kelvin source of both the IGBT i.e. let’s say current is flowing at the bottom winding of L1 (leaving dot terminal as shown in fig 2), current will flow into the dot terminal of the top winding of L1 which will make the IGBT to turn on fast, while the IGBT connected to L3 will make the IGBT to turn on slower ( just like a transformer action). So how does the common mode choke make the IGBT in parallel share the current equally? (as shown in the below figure)

                                              Fig. 2

2) It is said in one of the e2e question and answer section that the resistor R34 and R35 offers a low impedance / short circuit path across the winding of the CM choke for the short circuit transients to be detected by DESAT circuit. But what is stopping the differential current (gate drive current) from flowing through R34 ( https://e2e.ti.com/support/tools/simulation-hardware-system-design-tools-group/sim-hw-system-design/f/simulation-hardware-system-design-tools-forum/1061902/tida-00917-igbt-gate-driver---cm-choke-sizing-and-current-rating ) . If that happens, doesn’t the common mode choke saturate?

3) R9 and R21 shown in Fig. 1, are used to reduce the circulating current as shown in the below Fig 3. But if it is used, doesn’t that affect the DESAT circuit and may affect the desat voltage that was set?

                                Fig. 3

  • 0
    TI__Intellectual 1600 points

    Hi Vijaymahantesh,

    Thank you for reaching out to us on the TIDA-00917.

    (1) In your fig (2) you did not mention the source by which this current has come from. Anyway, if such a 'transient' current does occur, it will generate a same voltage on both high-side and low-side of L1, as L1 is a common mode choke. L1 will present a high resistance to this current and make it small to afftec the gate driving voltage. We can refer to the circuit in your fig (3) for it: when resistances of Zpart1 and Zpart2 are high, the current in the loop will be low.

    (2) A common mode choke may saturate only when a high current flows through its winding. In short-circuit tests, the high currents in the main circuit will not go through this path, as the common mode chokes present a high impedance in the path, and thus the chokes will not get saturate.

    (3) DESAT detection has blank time for IGBT turn-on transient period. So it is no problem for R9 and R21 to be used here. 

    Best regards,

    Jerome Shan

  • 0 in reply to Jerome Shan
    Intellectual 301 points

    1) But doesn't it produce the same voltage, which will aggravate this problem? as shown n Fig.2.

    2) Let's say the gate current peak is 2 Amps. Why doesn't it flow through 0.01 ohms? If the gate current flows in a 0.01-ohm resistor, then the CM choke is not experiencing the same differential current in its windings. 

  • 0 in reply to Vijaymahantesh Surkod
    TI__Intellectual 1600 points

    1) No. The voltages induced from this current will be same on both sides of L1 and thus make the voltage on C34 not change. So no impacts on the gate driver circuit.

    2) Let's take L1 for example here. The gate charging current is a differential current for the common mode choke and thus L1 exhibs a very low impedance for this current. In this case, the gate charging current may not flow through the 0.01 ohm resistor, and it will not affect the gate driving circuit. On the other hand, the DESAT detect current does not go through the high side of L1 and thus the low side of L1 will have a very high impedance for it. In this case, we will need this 0.01 ohm resistor for the current to bypass L1.

  • 0 in reply to Jerome Shan
    Intellectual 301 points

    1) I have drawn the voltage induced (fig attached below) in the L1 and L3. Will it not add to gate voltage in L1 and subtract to gate voltage in L3 during dynamic conditions it means the IGBT which was turning on after will turn on more after and the other one slower which will make it even slower.

    2) The dc resistance of the CM choke ( B82789C0113N002) used in TID00917 is 250 mOhms and there is a parallel resistance added is 10 mOhms. Will CM choke provide impedance lower than 10 mOhm?

  • +1 in reply to Vijaymahantesh Surkod
    TI__Intellectual 1600 points

    1) On the one hand, both L1 and L3 will exhib high resistance to this current, if it does happen. On the other hand, as the voltage drops on both sides of L1 are same, the voltage on C34 will not change. Thus no influence on the gate driving. So is it in L3. 

    2) I am sorry for neglected the CM choke's dc resistance here. Nevertheless, it does not have influence on the conclusions above: the gate charging current will not be affected as it is a differential current for the CM chock, but the DESAT detect current will rely on this 0.01 Ohm resistor to bypass as the CM chock will show a high impedance to it.

  • 0 in reply to Jerome Shan
    Intellectual 301 points

    I have another question regarding the DESAT operation when SiC Discrete Mosfets are paralleled. If we connect both Mosfets drain to the desat pin (of course with associated circuitry) as shown in TIDA-00917, isn't it going to be a problem if the current sharing between the two SiC MOSFETs is not the same? Is there any extra circuit that has to be incorporated to avoid this problem that would occur due to different current sharing between the two, i.e., the MOSFET carrying more current will have more voltage (Vds), but the one with a low current will have lower voltage which effectively pulls the voltage (Vds) down? Isn't it going to be a problem when devices are paralleled?

  • 0 in reply to Jerome Shan
    Intellectual 301 points

    The CLMAP pin is left open in the design. While paralleling, do we have to keep this open or connect to Vee (to disable it)? or can it still be connected directly to both the gates of the devices (with equal trace length between the two gates to clamp pin?

  • +1 in reply to Vijaymahantesh Surkod
    TI__Intellectual 1600 points

    When the two device working in parallel does not share the current equally, the one flows more current may get higher Tj due to the higher current, then this higher Tj will lead to higher Rds(on) and make the current flows in this device to decrease. This is a natural negative feedback process. Without it, the two devices cannot work in parallel.

  • +1 in reply to Vijaymahantesh Surkod
    TI__Intellectual 1600 points

    Leave the CLAMP pin open is OK. When a negative power supply (VEE) is used in an application, CLAMP is usually no need.