PMP22343: +/-40-V Inverting Buck-Boost With Auxiliary Output Reference Design

I would also like to add that the case where even with no load the situation remains same at near 4.3 V going to CC. 

Eric Yue

Hello Naveen,

What is the total output power that you need to supply?  This design is only capable of 10 W loading so you may need to scale up the design if the +/-32 V outputs need to reach 2 A loading. Can you clarify the output current loading? What is the testing set up when you see the temperature rise?

Are you noticing switching waveforms at pins 8(SW)? if not there is a chance that the device you were testing was damaged. The enable threshold for TPS54560B is ~1.2V and tying the EN to VIN is okay in regards to voltage stress.

Thanks,

John

Hello John Dorosa

1. Output power is much less than 10 W. As I mentioned above, even with NO LOAD, the input DC supply moving to CC immediately crossing 4.3 V. As up to 4.3 V according to datasheet IC will be having UVLO protection. Even tried with load, 8 mA, still the supply is moving to CC immediately after crossing 4.3 V.

2. All parameters (Resistors, capacitors) are all as per TI reference schematic "PMP22343: Converter input going into CC protection under NO LOAD at output". There is no SC across any element in the circuit.

3. No, loading is not 2 A. 

4. Basically, even with NO LOAD, or LOAD with 8 mA still case remains the same as above.

5. Switching waveforms at 8 (SW) above 4.3 V (till 4.3 V there is ULVO condition with this IC) shows a high noise based with amplitude peak max 2 V.  

6. Even tried the circuit in Open loop, by removing R, C to COMP pin and then applying PWM pulse through function generator with 2V amplitude and frequency 150 kHz and duty cycle tested up to 50- 90% duty cycle .... Here input was upto 5.2 V however even with upper duty cycle limit, the output voltage is upto +/- 8 V only instead of +/-40 V ... This shouldn't have been the case if the IC was damaged. This rules out IC defective case.

Tried with every possibility as mentioned above. There is no resolution till now. 

Hi Naveen,

Can you double check the voltage rating on all of the ceramic caps? Please use the schematic on https://www.ti.com/tool/PMP22343 as reference, note that larger voltage ratings are needed for the input and boot cap.

What loading condition are you using for the open-loop testing? Is it possible to show more cycles?

Thanks,

John

Hii John Dorosa

Yes, indeed the above-mentioned schematic from TI only been used with all the caps ratings exactly same to this schematic... including the mag. of cap.

Loading in open loop its 5k ohms (8 mA) connected each between +40 and GND terminals and -40 and GND terminals.... 

Even with cycle repetition the waveform is same and is symmetric in each switching cycle.

I am not able to understand even with near unity duty cycles in open loop too with minimal loading the output is no way near 40 V .... Ultimately it is supposed to deliver +/-40 V in closed loop. Kindly help..

Hi Naveen,

Can you send me a copy of your design schematic? It would help with the debug process.

It may help to remove the diode from the positive output voltage loop and adjustthe feedback loop, effectively making the inverting buck-boost section only. Then we can add the positive output later.

I would like to see a switch node waveform for the open loop case. Also when running closed loop can you capture the VIN, EN, and BOOT pins? just to make sure the bias voltages are coming up okay.

Thanks,

John

Hii John Dorosa

1. Copy of design schematic

2. Captured DPO waveforms of RT/CLK(CH3), SW(CH2) , VIN(CH4) as shown above when run in open loop. Switch node waveform as shown above in open loop.

3. During closed loop till the input voltage 4.3 V the VIN and EN pin with respect to ground shows 4.3 V ....All other pins like SW, BOOT shows zero ..... As in closed loop as i have been saying immediately the input getting dropped once input crosses 4.3 V and at that point, VIN and EN shows same voltage where the voltage gets dropped like approx 0-1 V (Straight line).

whereas boot and SW pins shows some switching noise type waveform with peak-peak 2 V like that ... the shape shown above

Hii John Dorosa

Apologies, i gave input as pulse to COMP instead it should be a constant voltage... Just reverified and reconducted open loop performance testing.

Correct me if i am wrong... I tried to give a constant voltage of 1 V between COMP (when floating only after removing corresponding resistor and capacitor) Here input supply maximum was 5.1 V and once i started increasing input to COMP pin just near 1 V i can see again CC transfer of input supply and voltage at input dropped near to 1-1.5 V ..... All this happening in open loop 

Also, RT/CLK with respect to IC GND pin was zero even there is no input to COMP pin and even when tried to provide input to COMP pin ... both cases RT/CLK is showing zero only.

Hii John Dorosa

During retesting the following are the latest updates with the board ... Consider below kindly ignore above ones

1. During open loop testing at 5.1 V input and around 0.7 V applying directly across COMP pin and IC GND, there is an output voltage I can observe which is +/-41.2 Volts. Which seems to be positive outcome.

2. For the above case, At RT/CLK with respect to IC GND till 4.3 V there is 0 Volts and just above 4.3 V and no COMP pin voltage applied in open loop case , there I can see constant voltage of 500 mV and again once COMP pin voltage applied around 0.7 V i can observe below waveform.. Can you please clear is it correct or not? But frequency seem to be 78 kHz approx. however according to schematic, 150kHz should be switching frequency...

3. Further, when i tried to see drain-source voltage between SW as Source and VIN as Drain to check Vds of MOSFET, Supply is going to CC. Eventhough i have only used one channel of oscilloscope, i am unable to understand how its getting shorted.

Hi Naveen,

The UVLO for TPS54560B is 4.3V, I would not recommend operating around that voltage level. Section 7.4.1 of the datasheet for this device notes 4.5V as a minimum input voltage to operate with.

When the UVLO mode is activated the device goes through a start-up cycle. the lower frequency that you are seeing may be consecutive soft-start times that are re-enabling the device at a constant rate.

Does the design start up okay with in put voltage 4.5 - 5.5 V?

Thanks,

John

HII John Dorosa

Yeah as i have mentioned earlier i am aware of this 4.3 V UVLO .... yes the input voltage 4.5-5.5 V is showing +/-40 V in open loop as i have told in my last 2 comments... Kindly resolve the issue with closed loop one ... Open loop operation as above shows positive sign that no short circuit or damage of components .... still closed loop solution is not achieved with this schematic. 

Also, please comment on RT/CLK waveform shape in open loop as shown above. Is it correct?

Further, when i tried to see drain-source voltage between SW as Source and VIN as Drain to check Vds of MOSFET, Supply is going to CC. Even though i have only used one channel of oscilloscope, i am unable to understand how its getting shorted.

Hii John Dorosa

Input range is 4.5-5.5 V only ... wider voltage range is not required for our application.

Scope is non isolated ... However, i havent measured two different grounds on single scope .... Without using any kind of oscilloscope ,.... The CC condition prevails at above 4.3 V till now... As i said by utilising the same converter with COMP pin floated and giving reference of around 0.7 V at COMP pin the output i can clearly observe as +/-42.6 Volts.... The issue is in closed loop the IC should give +/-40V with input being 5 V ... which is still not happening in many of debugging sessions. Can you please the same at earliest.

Hi Naveen,

What is the loading condition when you are seeing the larger output voltages? Is the reference voltage 0.8V above the negative output voltage?

There is NO LOAD when i worked on open loop where output voltages are nearer to +/-40 V .... In closed loop even on NO LOAD as i have said in start itself the input is going to CC mode at more than 4.3 V input ..Reference voltage i am referring is at COMP pin and -40 V only.. not AGND.. Please resolve asap... 

Hii John Dorosa

You can check all the probabilities which all i have used in the above thread.

Hi Naveen,

So the issue is to do with the control loop/feedback. can you explain what VR3 is doing in your circuit? The image looks like either end is placed in parallel with the low side resistor and the wiper is left floating. If this is kept in the circuit you may force the circuit to try regulating a higher output voltage than 40V.

Is D2 a zener diode? or is this the same as D1 and D3?

Hii John Dorosa

VR3 is not present in the tested circuit from the start and only parallel resistor across VR3 is connected of 1K ohms value. D2 is zener diode of same part number which has been used by TI 43 V rating,... D1 and D3 are Schottky diodes with 80 V ratings