PMP22165: Sequencing doesn't match AMD Versal requirements

Tool/software:

Hello,

I am looking at using the TPS650861 PMIC IC in my design for Versal Power Management. I found this PMIC because it is used in the Power for Versal reference design (PMP22165).

I am noticing that the Versal power sequencing followed in the schematic design is not correct. The power up sequence does not follow AMD's requirements. I also notice that in the Test Report for the EVAL module, no power down sequence was reported. Looking at the design, I don't think this design meets the Versal power down sequencing either. Versal power down sequencing must be done in the reverse order as the power up sequence. 

Can clarity be provided on what the intended use of this EVAL board is? Was it designed for a different FPGA? If it was designed for the Versal as it is advertised, can someone explain why the sequence doesn't match what AMD requires? 

Thanks,

Ryan Larson