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Original question:

TIDA-010087: How to configure TIDA-010087 with other EVMs

TIDA-010087: Facing issue to interface ads131m08EVM with TI Micro TMS320F28388S by referring TIDA-010087

Ramakrishna Panda
Prodigy 90 points
Part Number: TIDA-010087
Other Parts Discussed in Thread: TMS320F28388S, ADS131M08

Tool/software:

Hi TI Team,

I am working on implementing the TIDA-010087 reference design and its software on a TMS320F28388S microcontroller, which is also part of the C2000 family. I have modified the provided code to fit my application, but I'm facing a critical issue:

  • When providing 1.2V input to CH0 (via a potentiometer), the ADC reading is only around 76 counts.
  • Simultaneously, CH1 shows a non-zero value despite no input being connected.

I have attached my modified code derived from TIDA-010087, along with oscilloscope waveforms for reference.

Additionally, I have two specific doubts:

  1. The ADS131M08 datasheet mentions that the DRDY pin triggers on the falling edge, but in my waveform, it appears to trigger on the rising edge.
  2. While the ADS131M08 supports SPI Mode 1, the TIDA-010087 example code uses SPI Mode 0. Could you please clarify this?


#include "driverlib.h"
#include "device.h"
#include "ads131m0x.h"

//-----------------------------------------------------------------------------
//
// External ADC communication GPIO configuration
//
//-----------------------------------------------------------------------------

#define BT2PH_EXT_ADC1_SDIN_GPIO_NUM 24
#define BT2PH_EXT_ADC1_SDIN_PIN_CONFIG GPIO_24_SPIB_SIMO

#define BT2PH_EXT_ADC1_SDOUT_GPIO_NUM 25
#define BT2PH_EXT_ADC1_SDOUT_PIN_CONFIG GPIO_25_SPIB_SOMI

#define BT2PH_EXT_ADC1_SCLK_GPIO_NUM 26
#define BT2PH_EXT_ADC1_SCLK_PIN_CONFIG GPIO_26_SPIB_CLK

#define BT2PH_EXT_ADC1_CS_GPIO_NUM 27
#define BT2PH_EXT_ADC1_CS_PIN_CONFIG_GPIO GPIO_27_GPIO27

#define BT2PH_EXT_ADC1_DRDY_GPIO_NUM 40
#define BT2PH_EXT_ADC1_DRDY_PIN_CONFIG_GPIO GPIO_40_GPIO40

#define BT2PH_EXT_ADC1_RST_GPIO_NUM 41
#define BT2PH_EXT_ADC1_RST_PIN_CONFIG_GPIO GPIO_41_GPIO41

//
// External ADC DRDY Interrupt configuration
//

#define BT2PH_EXT_ADC1_INT_DRDY INT_XINT1
#define BT2PH_EXT_ADC1_ISR_DRDY ISR4
#define BT2PH_EXT_ADC1_INT_DRDY_INTERRUPT_ACK_GROUP INTERRUPT_ACK_GROUP1

//
// External ADC SPI Interrupt configuration
//
#define BT2PH_EXT_ADC1_SPI_CLOCK_FREQ_HZ         (1000000U)
#define BT2PH_EXT_ADC1_SPI_BASE SPIB_BASE
#define BT2PH_EXT_ADC1_INT_SPI_RX INT_SPIB_RX
#define BT2PH_EXT_ADC1_ISR_SPI_RXFIFO ISR7
#define BT2PH_EXT_ADC1_SPI_RXFIFO_INTERRUPT_ACK_GROUP INTERRUPT_ACK_GROUP6

#define BT2PH_TEST_GPIO                  31
#define BT2PH_TEST_GPIO_PIN_CONFIG            GPIO_31_GPIO31

//
// EPWM configuration for Ext ADC CLK
//
#define BT2PH_EXT_ADC1_CLK_EPWM_BASE                 EPWM5_BASE
#define BT2PH_EXT_ADC1_CLK_EPWM_NUM                  ((uint16_t)5)
#define BT2PH_EXT_ADC1_CLK_EPWM_GPIO_NUM               ((uint16_t)8)
#define BT2PH_EXT_ADC1_CLK_PIN_CONFIG_EPWM    GPIO_8_EPWM5A
#define BT2PH_EXT_ADC1_CLK_PIN_CONFIG_GPIO    GPIO_8_GPIO8

//
// Set ADC clock to 8MHz
//
#define BT2PH_EXT_ADC1_CLK_EPWM_PERIOD_TICKS         ((uint32_t)(12))
#define BT2PH_EXT_ADC1_CLK_EPWM_PERIOD                ((uint32_t)(BT2PH_EXT_ADC1_CLK_EPWM_PERIOD_TICKS - 1))



//*****************************************************************************
void BT2PH_HAL_disableEpwmCounting(void);
void BT2PH_HAL_enableEpwmCounting(void);
void BT2PH_HAL_setupGpioExtAdcClk(void);
void BT2PH_HAL_setupEpwmExtAdcClk(void);
void BT2PH_HAL_SetupSpiGpio(void);
void BT2PH_HAL_SetupSpi(void);

void BT2PH_HAL_setupGpioExtAdc(void);
void BT2PH_HAL_setupExtAdc(void);
void BT2PH_HAL_setupIntAdcInterrupt(void);
void BT2PH_HAL_enableIntAdcInterrupt(void);
void BT2PH_HAL_setupExtAdcInterrupt(void);
void BT2PH_HAL_enableExtAdcInterrupt(void);
void BT2PH_HAL_enableGlobalInterrupt(void);
void delay_ms(const uint32_t);

volatile uint16_t BT2PH_ExtAdcRxflag1 ;
ads131m0x_data  BT2PH_ExtAdc1;

void BT2PH_HAL_GpioWrite(uint32_t GPIO_NUM, uint16_t state)
{
    GPIO_writePin(GPIO_NUM, state & 0x01);
}

static inline void BT2PH_HAL_ExtAdcTxframe(uint32_t base){
    //set CS low before this function
    //send bytes for N channel data read
    uint16_t crcWordIn =0;
// send null word
    HWREGH(base + SPI_O_TXBUF) = 0x0000;
//send CRC if enabled, otherwise write 0
    HWREGH(base + SPI_O_TXBUF) = crcWordIn;

//send rest 8 words
    HWREGH(base + SPI_O_TXBUF) = 0x0000;
    HWREGH(base + SPI_O_TXBUF) = 0x0000;
    HWREGH(base + SPI_O_TXBUF) = 0x0000;
    HWREGH(base + SPI_O_TXBUF) = 0x0000;
    HWREGH(base + SPI_O_TXBUF) = 0x0000;
    HWREGH(base + SPI_O_TXBUF) = 0x0000;
    HWREGH(base + SPI_O_TXBUF) = 0x0000;
    HWREGH(base + SPI_O_TXBUF) = 0x0000;

}

static inline void BT2PH_HAL_ExtAdcRxframe(ads131m0x_data *DataStruct,
                                           uint32_t base){

    //
    // read from the buffer
    //
    DataStruct->response=HWREGH(base + SPI_O_RXBUF);

    DataStruct->channel0= HWREGH(base + SPI_O_RXBUF);
    DataStruct->channel1=HWREGH(base + SPI_O_RXBUF);
    DataStruct->channel2=HWREGH(base + SPI_O_RXBUF);
    DataStruct->channel3=HWREGH(base + SPI_O_RXBUF);
    DataStruct->channel4=HWREGH(base + SPI_O_RXBUF);
    DataStruct->channel5=HWREGH(base + SPI_O_RXBUF);
    DataStruct->channel6=HWREGH(base + SPI_O_RXBUF);
    DataStruct->channel7=HWREGH(base + SPI_O_RXBUF);
    DataStruct->crc=HWREGH(base + SPI_O_RXBUF);

}

#pragma FUNC_ALWAYS_INLINE(BT2PH_HAL_ExtAdcSendTxFrame)
static inline void BT2PH_HAL_ExtAdcSendTxFrame(void){
    //
    // data is available in the FIFO to read
    //
    if(BT2PH_ExtAdcRxflag1==1)
    {
        BT2PH_ExtAdcRxflag1 =0;

        //
        // make cs low and send the data
        //
        GPIO_writePin(BT2PH_EXT_ADC1_CS_GPIO_NUM, 0);

        //
        //send command to read data
        //
        BT2PH_HAL_ExtAdcTxframe(BT2PH_EXT_ADC1_SPI_BASE);

    }

}

#pragma FUNC_ALWAYS_INLINE(BT2PH_HAL_DrdyGpioAckInterrupt)
static inline void BT2PH_HAL_DrdyGpioAckInterrupt(void){
    Interrupt_clearACKGroup(BT2PH_EXT_ADC1_INT_DRDY_INTERRUPT_ACK_GROUP);
}

#pragma FUNC_ALWAYS_INLINE(BT2PH_HAL_ExtAdcRead)
static inline void BT2PH_HAL_ExtAdcRead(){
    //
    // make cs high
    //
    GPIO_writePin(BT2PH_EXT_ADC1_CS_GPIO_NUM, 1);
    BT2PH_HAL_ExtAdcRxframe(&BT2PH_ExtAdc1,BT2PH_EXT_ADC1_SPI_BASE);

    //
    // flag to hold receive is complete
    //
    BT2PH_ExtAdcRxflag1=1;

}

#pragma FUNC_ALWAYS_INLINE(BT2PH_HAL_SpiRxFifoAckInterrupt)
static inline void BT2PH_HAL_SpiRxFifoAckInterrupt(){
    SPI_clearInterruptStatus(BT2PH_EXT_ADC1_SPI_BASE, SPI_INT_RXFF );
    Interrupt_clearACKGroup(BT2PH_EXT_ADC1_SPI_RXFIFO_INTERRUPT_ACK_GROUP);
}



void main(void)
{

    //
    // Initialize device clock and peripherals
    // Device clock is set 120MHz
    //
    Device_init();

    //
    // Disable pin locks and enable internal pullups.
    //
    Device_initGPIO();

    //
    // Initialize PIE and clear PIE registers. Disables CPU interrupts.
    //
    Interrupt_initModule();

    //
    // Initialize the PIE vector table with pointers to the shell Interrupt
    // Service Routines (ISR).
    //
    Interrupt_initVectorTable();


    EALLOW;


    //
    // Clock for External ADC - GPIO pin configuration to EPWM
    //
    BT2PH_HAL_setupGpioExtAdcClk();

    //
    // Clock for External ADC- ePWM setup
    //
    BT2PH_HAL_disableEpwmCounting();
    BT2PH_HAL_setupEpwmExtAdcClk();
    BT2PH_HAL_enableEpwmCounting();


    //
    // Configure SPI for External ADC1
    // Initialize External ADC1
    //
    BT2PH_HAL_SetupSpiGpio();
    BT2PH_HAL_SetupSpi();

    BT2PH_HAL_setupGpioExtAdc();
    BT2PH_HAL_setupExtAdc();


    //
    // Initialize global variables used in the solution
    //
//    BT2PH_initUserVariables();
//    BT2PH_initProgramVariables();
//    BT2PH_setControlCoeffcients();

    //
    // Configure and enable External ADC dataready and SPI interrupt
    //
    BT2PH_HAL_setupExtAdcInterrupt();
    BT2PH_HAL_enableExtAdcInterrupt();



    //
    // enable global interrupts
    //
    BT2PH_HAL_enableGlobalInterrupt();

    EDIS;

    //
    // Send ExtAdc transmit frame
    //
    BT2PH_HAL_ExtAdcTxframe(BT2PH_EXT_ADC1_SPI_BASE);




    for(;;)
    {
        //
        // Background state machine entry & exit point
        //

    }

} // END MAIN CODE

// ISR4() interrupt function
//
#pragma CODE_SECTION(ISR4,"isrcodefuncs");
#pragma INTERRUPT(ISR4, HPI)
interrupt void ISR4(void)
{
    //
    // ISR is triggered by DRDY
    //

    BT2PH_HAL_ExtAdcSendTxFrame();


    BT2PH_HAL_GpioWrite(BT2PH_TEST_GPIO,1);
    //BT2PH_runPwmIsr();
    BT2PH_HAL_GpioWrite(BT2PH_TEST_GPIO,0);

    BT2PH_HAL_DrdyGpioAckInterrupt();

}

//
// ISR6() interrupt function
//
#pragma CODE_SECTION(ISR7,"isrcodefuncs");
#pragma INTERRUPT(ISR7, HPI)
interrupt void ISR7(void)
{
    //
    // ISR is triggered by the SPIB_RX
    //
    BT2PH_HAL_ExtAdcRead();
    BT2PH_HAL_SpiRxFifoAckInterrupt();

}


void BT2PH_HAL_setupExtAdc(void)
{

    //
    //(OPTIONAL) Provide additional delay time for power supply settling
    //
    delay_ms(50);

    //
    //(REQUIRED) Set nRESET pin high for ADC operation
    //

    GPIO_writePin(BT2PH_EXT_ADC1_RST_GPIO_NUM, 1);
    delay_ms(1);

    //
    //(OPTIONAL) Toggle nRESET pin to ensure default register settings
    //NOTE: This also ensures that the device registers are unlocked.
    //

//    GPIO_writePin(BT2PH_EXT_ADC1_RST_GPIO_NUM, 0);
//    delay_ms(1);
//    GPIO_writePin(BT2PH_EXT_ADC1_RST_GPIO_NUM, 1);
//    delay_ms(1);


    //
    //(REQUIRED) Configure MODE register settings
    //

    while(!GPIO_readPin(BT2PH_EXT_ADC1_DRDY_GPIO_NUM));

    //
    // set CSn to Low
    //
    GPIO_writePin(BT2PH_EXT_ADC1_CS_GPIO_NUM, 0);

    SPI_writeDataBlockingFIFO(BT2PH_EXT_ADC1_SPI_BASE, MODE_VALUE_RESET_SPI2);
    SPI_readDataBlockingFIFO(BT2PH_EXT_ADC1_SPI_BASE);

    SPI_writeDataBlockingFIFO(BT2PH_EXT_ADC1_SPI_BASE, MODE_VALUE_RESET_SPI1);
    SPI_readDataBlockingFIFO(BT2PH_EXT_ADC1_SPI_BASE);

    SPI_writeDataBlockingFIFO(BT2PH_EXT_ADC1_SPI_BASE, MODE_VALUE_RESET_SPI0);
    SPI_readDataBlockingFIFO(BT2PH_EXT_ADC1_SPI_BASE);

    //
    // set CSn to High
    //
    GPIO_writePin(BT2PH_EXT_ADC1_CS_GPIO_NUM, 1);

    SysCtl_delay(10000);


    //
    // CSn to Low
    //
    GPIO_writePin(BT2PH_EXT_ADC1_CS_GPIO_NUM, 0);
    SPI_writeDataBlockingFIFO(BT2PH_EXT_ADC1_SPI_BASE,
                              MODE_VALUE_PROGRAMMED_SPI2);
    SPI_readDataBlockingFIFO(BT2PH_EXT_ADC1_SPI_BASE);

    SPI_writeDataBlockingFIFO(BT2PH_EXT_ADC1_SPI_BASE,
                              MODE_VALUE_PROGRAMMED_SPI1);
    SPI_readDataBlockingFIFO(BT2PH_EXT_ADC1_SPI_BASE);

    SPI_writeDataBlockingFIFO(BT2PH_EXT_ADC1_SPI_BASE,
                              MODE_VALUE_PROGRAMMED_SPI0);
    SPI_readDataBlockingFIFO(BT2PH_EXT_ADC1_SPI_BASE);

    //
    // set CSn to High
    //
    GPIO_writePin(BT2PH_EXT_ADC1_CS_GPIO_NUM, 1);

    SysCtl_delay(10000);

    //
    // CSn to Low
    //
    GPIO_writePin(BT2PH_EXT_ADC1_CS_GPIO_NUM, 0);
    SPI_writeDataBlockingFIFO( BT2PH_EXT_ADC1_SPI_BASE,
                               CLOCK_VALUE_PROGRAMMED_SPI2);
    SPI_readDataBlockingFIFO(BT2PH_EXT_ADC1_SPI_BASE);

    SPI_writeDataBlockingFIFO(BT2PH_EXT_ADC1_SPI_BASE,
                              CLOCK_VALUE_PROGRAMMED_SPI1);
    SPI_readDataBlockingFIFO(BT2PH_EXT_ADC1_SPI_BASE);

    SPI_writeDataBlockingFIFO(BT2PH_EXT_ADC1_SPI_BASE,
                              CLOCK_VALUE_PROGRAMMED_SPI0);
    SPI_readDataBlockingFIFO(BT2PH_EXT_ADC1_SPI_BASE);

    //
    // set CSn to High
    //
    GPIO_writePin(BT2PH_EXT_ADC1_CS_GPIO_NUM, 1);

    SysCtl_delay(10000);

}
void BT2PH_HAL_SetupSpi(void)
{
    //
    // Must put SPI into reset before configuring it
    //
    SPI_disableModule(BT2PH_EXT_ADC1_SPI_BASE);
    //
    // SPI configuration. Use a 1MHz SPICLK and 16-bit word size.
    //
    SPI_enableHighSpeedMode(BT2PH_EXT_ADC1_SPI_BASE);
    SPI_setConfig(BT2PH_EXT_ADC1_SPI_BASE,
                  SysCtl_getLowSpeedClock(DEVICE_OSCSRC_FREQ),
                  SPI_PROT_POL0PHA0,
                  SPI_MODE_CONTROLLER, BT2PH_EXT_ADC1_SPI_CLOCK_FREQ_HZ, 16);


    SPI_setEmulationMode(BT2PH_EXT_ADC1_SPI_BASE, SPI_EMULATION_STOP_MIDWAY);
    SPI_enableFIFO(BT2PH_EXT_ADC1_SPI_BASE);

    SPI_clearInterruptStatus(BT2PH_EXT_ADC1_SPI_BASE,
                             SPI_INT_RX_DATA_TX_EMPTY
                             |SPI_INT_RXFF|SPI_INT_TXFF );

    SPI_setFIFOInterruptLevel(BT2PH_EXT_ADC1_SPI_BASE,
                              SPI_FIFO_TX0, SPI_FIFO_RX10);

    SPI_enableInterrupt(BT2PH_EXT_ADC1_SPI_BASE, SPI_INT_RXFF|SPI_INT_TXFF);

    //
    // Configuration complete. Enable the module.
    //
    SPI_enableModule(BT2PH_EXT_ADC1_SPI_BASE);

}

void BT2PH_HAL_SetupSpiGpio(void){

    //
    // Configure SPI GPIO pins for SPIB
    //
    GPIO_setQualificationMode(BT2PH_EXT_ADC1_SDIN_GPIO_NUM, GPIO_QUAL_ASYNC);
    GPIO_setQualificationMode(BT2PH_EXT_ADC1_SDOUT_GPIO_NUM, GPIO_QUAL_ASYNC);
    GPIO_setQualificationMode(BT2PH_EXT_ADC1_SCLK_GPIO_NUM, GPIO_QUAL_ASYNC);
    GPIO_setPinConfig(BT2PH_EXT_ADC1_SDIN_PIN_CONFIG);
    GPIO_setPinConfig(BT2PH_EXT_ADC1_SDOUT_PIN_CONFIG);
    GPIO_setPinConfig(BT2PH_EXT_ADC1_SCLK_PIN_CONFIG);

    //
    //Configure CSn pin for ADS131M0x
    //
    //
    // Enable pullup on GPIO6
    //
    GPIO_setPadConfig(BT2PH_EXT_ADC1_CS_GPIO_NUM, GPIO_PIN_TYPE_PULLUP);

    GPIO_writePin(BT2PH_EXT_ADC1_CS_GPIO_NUM, 1);
    GPIO_setPinConfig(BT2PH_EXT_ADC1_CS_PIN_CONFIG_GPIO);
    GPIO_setDirectionMode(BT2PH_EXT_ADC1_CS_GPIO_NUM, GPIO_DIR_MODE_OUT);
}

void BT2PH_HAL_setupGpioExtAdc(void)
{

    // Configure HWINT GPIO for External Adc DRDY pin

    GPIO_setPinConfig(BT2PH_EXT_ADC1_DRDY_PIN_CONFIG_GPIO);
    GPIO_setDirectionMode(BT2PH_EXT_ADC1_DRDY_GPIO_NUM, GPIO_DIR_MODE_IN);
    GPIO_setQualificationMode(BT2PH_EXT_ADC1_DRDY_GPIO_NUM, GPIO_QUAL_SYNC);


    GPIO_setInterruptPin(BT2PH_EXT_ADC1_DRDY_GPIO_NUM, GPIO_INT_XINT1);

    //
    // Configure XINT1 to be a triggered by a falling edge
    //
    GPIO_setInterruptType(GPIO_INT_XINT1, GPIO_INT_TYPE_FALLING_EDGE);

    //
    // Enable XINT1
    //
    GPIO_enableInterrupt(GPIO_INT_XINT1);

    // Configure Reset pin for the External ADC
    GPIO_setPadConfig(BT2PH_EXT_ADC1_RST_GPIO_NUM, GPIO_PIN_TYPE_PULLUP);
    GPIO_writePin(BT2PH_EXT_ADC1_RST_GPIO_NUM, 1);
    GPIO_setPinConfig(BT2PH_EXT_ADC1_RST_PIN_CONFIG_GPIO);
    GPIO_setDirectionMode(BT2PH_EXT_ADC1_RST_GPIO_NUM, GPIO_DIR_MODE_OUT);
}
void BT2PH_HAL_enableExtAdcInterrupt(void)
{
    Interrupt_enable(BT2PH_EXT_ADC1_INT_DRDY);

    SPI_resetRxFIFO(BT2PH_EXT_ADC1_SPI_BASE);
    SPI_resetTxFIFO(BT2PH_EXT_ADC1_SPI_BASE);
    SPI_clearInterruptStatus(BT2PH_EXT_ADC1_SPI_BASE, SPI_INT_RXFF );
    Interrupt_enable(BT2PH_EXT_ADC1_INT_SPI_RX);

}
void BT2PH_HAL_setupExtAdcInterrupt(void)
{
    Interrupt_register(BT2PH_EXT_ADC1_INT_DRDY, &BT2PH_EXT_ADC1_ISR_DRDY);
    Interrupt_register(BT2PH_EXT_ADC1_INT_SPI_RX,
                       &BT2PH_EXT_ADC1_ISR_SPI_RXFIFO);

}
void BT2PH_HAL_enableGlobalInterrupt(void){

    EALLOW;
    EINT;  // Enable Global interrupt INTM
    ERTM;  // Enable Global real-time interrupt DBGM
    EDIS;
}
void delay_ms(const uint32_t delay_time_ms)
{
    SysCtl_delay(delay_time_ms * SysCtl_getClock(DEVICE_LSPCLK_FREQ)* 1000u);
}

void BT2PH_HAL_enableEpwmCounting(void)
{
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);
}

void BT2PH_HAL_disableEpwmCounting(void){

    SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);
}
void BT2PH_HAL_setupGpioExtAdcClk(void){
    GPIO_writePin(BT2PH_EXT_ADC1_CLK_EPWM_GPIO_NUM, 0);
    GPIO_setDirectionMode(BT2PH_EXT_ADC1_CLK_EPWM_GPIO_NUM, GPIO_DIR_MODE_OUT);
    GPIO_setPinConfig(BT2PH_EXT_ADC1_CLK_PIN_CONFIG_EPWM);
    GPIO_setQualificationMode(BT2PH_EXT_ADC1_CLK_EPWM_GPIO_NUM, GPIO_QUAL_SYNC);
}

//
// BT2PH_HAL_setupEpwmExtAdcClk - Configure EPWM for External ADC CLK
//

void BT2PH_HAL_setupEpwmExtAdcClk(void){


    //
    // Maximum supported ePWM clock speed is specified in the datasheet
    //

    EPWM_setClockPrescaler(BT2PH_EXT_ADC1_CLK_EPWM_BASE,
                           EPWM_CLOCK_DIVIDER_1,
                           EPWM_HSCLOCK_DIVIDER_1);

    EPWM_setEmulationMode(BT2PH_EXT_ADC1_CLK_EPWM_BASE, EPWM_EMULATION_FREE_RUN);


    //
    // Configure ePWM for count-up operation
    //
    EPWM_setTimeBaseCounter(BT2PH_EXT_ADC1_CLK_EPWM_BASE, 0);
    EPWM_setTimeBasePeriod(BT2PH_EXT_ADC1_CLK_EPWM_BASE,
                           BT2PH_EXT_ADC1_CLK_EPWM_PERIOD);
    EPWM_setPeriodLoadMode(BT2PH_EXT_ADC1_CLK_EPWM_BASE,
                           EPWM_PERIOD_SHADOW_LOAD);
    EPWM_setTimeBaseCounterMode(BT2PH_EXT_ADC1_CLK_EPWM_BASE,
                                EPWM_COUNTER_MODE_UP);
    EPWM_disablePhaseShiftLoad(BT2PH_EXT_ADC1_CLK_EPWM_BASE);

    //
    // Set Compare values for 50% duty cycle
    //
    EPWM_setCounterCompareValue(BT2PH_EXT_ADC1_CLK_EPWM_BASE,
                                EPWM_COUNTER_COMPARE_A,
                                BT2PH_EXT_ADC1_CLK_EPWM_PERIOD/2);

    //
    // Use shadow mode to update CMPA on TBPRD
    //
    EPWM_setCounterCompareShadowLoadMode(BT2PH_EXT_ADC1_CLK_EPWM_BASE,
                                         EPWM_COUNTER_COMPARE_A,
                                         EPWM_COMP_LOAD_ON_CNTR_PERIOD);


    //
    // Configure Action Qualifier SubModule to:
    //
    // Use shadow mode to update AQCTL
    //
    EPWM_setActionQualifierShadowLoadMode(BT2PH_EXT_ADC1_CLK_EPWM_BASE,
                                          EPWM_ACTION_QUALIFIER_A,
                                          EPWM_AQ_LOAD_ON_CNTR_PERIOD);
    EPWM_setActionQualifierAction(BT2PH_EXT_ADC1_CLK_EPWM_BASE,
                                  EPWM_AQ_OUTPUT_A,
                                  EPWM_AQ_OUTPUT_HIGH,
                                  EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);

    EPWM_setActionQualifierAction(BT2PH_EXT_ADC1_CLK_EPWM_BASE,
                                      EPWM_AQ_OUTPUT_A,
                                      EPWM_AQ_OUTPUT_LOW,
                                      EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);



}

  • 0
    TI__Intellectual 1880 points

    Hi Ramakrishna,


    ADS131M08 transmits the data at the rising edge of the SCLK and receive at the falling edge. Therefore, C2000 needs to programmed to receive the data at falling edge, and transmit the data at the rising. This mode is SPI-00 in the C2000 real-time microcontrollers. Please see the below picture. You can read more about in the technical reference manual.

    The DRDY pin of the ADS131M08 ADC is active low output. When the ADC is working in the continuous conversion mode, you are expecting to see below waveform. Below is the CS and DRDY waveform when ADC is running at 16kSPS. From your waveform it seem like ADS131M08 is not programmed correctly. I have forwarded this thread to the application engineer who supports ADS131M08.

    Regards,

    Shaury

  • 0 in reply to Shaury Anand
    Prodigy 90 points

    Hi Shaury,

    Thanks for your response.

    Update: The DRDY waveform is now appearing correctly (active low output).
    However, the issue with incorrect data still persists, as mentioned earlier.
    We hope the Application Engineer can respond promptly, as this is critical for the project.

    Regards,
    Ramakrishna 


  • 0 in reply to Ramakrishna Panda
    TI__Intellectual 1880 points

    Hi Ramakrishna,

    We need more clarification on the issue. Are you able to read ADS131M08 register using C2000? You can try reading ID register, and compare the ADC output latched in the C2000 with logic analyzer. If you not able to read correctly, could you share SPI waveforms?

    Regards,
    Shaury

  • 0 in reply to Shaury Anand
    Prodigy 90 points

    Hi Shaury,

    Thank you for your response.

    I'm facing an issue with reading the ADS131M08 register using C2000. Our logic analyzer is showing some issues, so I have attached an oscilloscope snapshot and a video for reference. Additionally, I've included my functions, EXT_ADC1_verifyMode() and EXT_ADC1_verifyID(), for your review.

    Could you please advise if there's anything missing in my register reading functions?

    NOTE: Complete code is added in trail message .

    Thank you,
    Ramakrishna

    #define ADDR_ID_REG        (0x00)
#define ADDR_STATUS_REG    (0x01)
#define ADDR_MODE_REG      (0x02)
#define ADDR_CLOCK_REG     (0x03)

#define RREG_COMMAND_ID     ((0x0005 << 13) | (ADDR_ID_REG << 7))
#define RREG_COMMAND_MODE   ((0x0005 << 13) | (ADDR_MODE_REG << 7))

uint8_t EXT_ADC1_verifyID(void)
{
    uint16_t device_id = 0;
    uint16_t response = 0;
    
    // Wait for DRDY to be ready
    while(!GPIO_readPin(BT2PH_EXT_ADC1_DRDY_GPIO_NUM));
    
    // Set CSn to Low to start communication
    GPIO_writePin(BT2PH_EXT_ADC1_CS_GPIO_NUM, 0);
    
    // Send RREG command to read ID register
    SPI_writeDataBlockingFIFO(BT2PH_EXT_ADC1_SPI_BASE, RREG_COMMAND_ID);
    response = SPI_readDataBlockingFIFO(BT2PH_EXT_ADC1_SPI_BASE);
    
    // Read the ID register value (dummy write to receive data)
    SPI_writeDataBlockingFIFO(BT2PH_EXT_ADC1_SPI_BASE, 0x0000);
    device_id = SPI_readDataBlockingFIFO(BT2PH_EXT_ADC1_SPI_BASE);
    
    // Set CSn to High to end communication
    GPIO_writePin(BT2PH_EXT_ADC1_CS_GPIO_NUM, 1);
    
    // Check if device ID matches expected value for ADS131M08
    // The datasheet indicates device ID should be 0x08 for ADS131M08
    uint8_t id_valid = ((device_id & 0x00FF) == 0x08);
    
    // Print verification result with timestamp and user info
    printf("ID Verification: Read ID=0x%04X, Expected=0x0008, %s\n", 
           device_id, id_valid ? "SUCCESS" : "FAILED");
    
    return id_valid;
}

uint8_t EXT_ADC1_verifyMode(void)
{
    uint16_t mode_value = 0;
    uint16_t response = 0;
    
    // Wait for DRDY to be ready
    while(!GPIO_readPin(BT2PH_EXT_ADC1_DRDY_GPIO_NUM));
    
    // Set CSn to Low to start communication
    GPIO_writePin(BT2PH_EXT_ADC1_CS_GPIO_NUM, 0);
    
    // Send RREG command to read MODE register
    SPI_writeDataBlockingFIFO(BT2PH_EXT_ADC1_SPI_BASE, RREG_COMMAND_MODE);
    response = SPI_readDataBlockingFIFO(BT2PH_EXT_ADC1_SPI_BASE);
    
    // Read the MODE register value (dummy write to receive data)
    SPI_writeDataBlockingFIFO(BT2PH_EXT_ADC1_SPI_BASE, 0x0000);
    mode_value = SPI_readDataBlockingFIFO(BT2PH_EXT_ADC1_SPI_BASE);
    
    // Set CSn to High to end communication
    GPIO_writePin(BT2PH_EXT_ADC1_CS_GPIO_NUM, 1);
    
    // Check if mode value matches expected programmed value
    uint8_t mode_valid = (mode_value == REG_MODE_VALUE_PROGRAMMED);
    
    // Print verification result with timestamp and user info
    printf("MODE Verification: Read Mode=0x%04X, Expected=0x%04X, %s\n", 
           mode_value, REG_MODE_VALUE_PROGRAMMED, mode_valid ? "SUCCESS" : "FAILED");
    
    return mode_valid;
}

  • 0 in reply to Ramakrishna Panda
    Prodigy 90 points

    Hi Shaury,

    I am waiting for your feedback .

    Regards,
    Ramakrishna

  • 0 in reply to Ramakrishna Panda
    TI__Intellectual 1880 points

    Hi Ramakrishna,

    It is difficult to see the from the video that ADS131M08 response. Could you trigger the oscilloscope on CS and ADS131M08 SDO pin output in single shot mode? For time being you just forget about DRDY, just read ID register, and confirm the SDO response matching the datasheet.

    Regards,
    Shaury

  • 0 in reply to Shaury Anand
    TI__Intellectual 1880 points

    Hi Ramakrishna,

    I looked at the code. For register read and write, you don't need to poll the DRDY signal. DRDY tells you when ADC conversion data is available for read. Try the SPI command as described in the datasheet, and see the what you are reading the OSCILLOSCOPE, and confirm if it matches in what you reading in the C2000 MCU. If you can verify the interface is working, the next step is to program in the desired operating settings for the ADC.

    // Wait for DRDY to be ready
    while(!GPIO_readPin(BT2PH_EXT_ADC1_DRDY_GPIO_NUM));

    Regards,

    Shaury