TIDA-01606: Hardware Design Questions

Noah,

1. We wanted to showcase a fully isolated design. Although, this is not required for all application.  It's up to you.

2. this is based on our requirement to support 230Vrms phase voltage input.  this is good enough for our requirement

3. same reason here to support 230Vrms phase voltage

4.  the AEF is a placeholder for future testing.  separating V_SN_N and V_PCC_N help with from a filter & voltage sensing perspective.  V_PCC_N isn't meant to be a return point for common mode noise in this design, we're using it for phase voltage sensing on the grid side.

5. those caps help with reducing return loop.  it's more visible when you examine the layout.  for the vdc+ to vdc_mid, due to the relative placement, it doesn't really help much.

6. the clk buffer ensures we get good signal integrity for long traces

7. yes, for common mode noise return relative to VDC_MID

-Kelvin

Hi Kelvin,

Thank you for the reply. I understand most of the above answers. Thank you for those.

Can you please explain how the AEF is a placeholder for future testing? How is separating V_SN_N and V_PCC_N help from a filter perspective? Are you referring to the choice of a single device with respect from Line to the virtual GND (such as GRID_GND) would then produce Common-mode return path for the each phase bridge out to the grid. So you use the separated nodes V_SN_N and V_PCC_N to create sensing of the grid voltage and common-mode return of the EMI filter of each phase?

If you were to update this design for a 440VAC L-L application the MOVs and Film X Capacitors would need to be updated to a higher voltage rating?

C74 and C80 are being utilized as Y capacitors?

Noah,

the AEF is not being supported right now.  we need to keep that circuit somewhat isolated from the other circuits when the AEF is disabled. this is good practice for debugging a new design. make it easier to debug if things go wrong.

if you look at the location of V_PCC_N, the only function of that point is a reference point for voltage sensing.  The MOVs are not active during normal operation.  If you consider tying the V_SN_N and V_PCC_N together, think about the noise coupling from the switching node neutral to the grid side PCC neutral.  since you want to measure a clean grid phase voltage you would want to have a clean neutral reference.  I think if you want to tie V_SN_N and V_PCC_N together, you will need to have a low impedance path from the lines to the V_PCC_N for it to make sense.  Because right now the the impedance from the PCC lines to the  V_PCC_N is very high (not meant to be a filter).  If course, you can convince yourself with a SPICE simulation to see if it helps.

Right now, the design basically have an LCL filter configuration. you can always get creative with it.

IsoM5-275 supports a max continuous AC voltage of 275Vrms (see datasheet).  We specified a max rated VLL of 400V (~230Vrms phase voltage) for this design to allow some margin for transients on the line.  If you have 440VLL, that means you have 254Vrms phase voltage nominal.  Do you expect the line voltage to be under 275Vrms for normal operation? this is the question you have to ask.  If you need more you can pick the next device like IsoM5-300.

The same analysis can be done with capacitors.

C74 and C80 are connected to earth so yes they're used as Y caps.

Hi Kelvin,

These helped answer my questions. Thank you. My source is Delta Connected not Wye Connected so I will need to utilize larger MOV and Caps.

Regards,

-Noah