TPS55289: TPS55289

Weng Tzannbor

Prodigy 40 points

Part Number: TPS55289

Tool/software:

Dear TI's team members,

Driving Condition for Buck-Boost PWM IC :

Input Voltage = 12V

Output Voltage = 6.5V ( +/-5% )

Load Current (max.) = 1mA ~ 4A

Voltage Ripple = (+/-) 325mV

Could you provide us some feedback about this gain margin & phase margin based on TI's SPICE modeling ?

Thanks & Best Regards !!

8 months ago

+1 Aurora Tie 8 months ago

TI__Genius 17990 points

Hi,

Bryce will give you feedback these two days. Thanks for your patience.

Aurora

+1 Bryce Xun 8 months ago

TI__Mastermind 28720 points

Hi Tzannbor,

Thanks for reaching out.

The gain margin and phase margin can be read from the bode plot result in the attached Calculation Tool, you can fill in the table and especially take care of the output effective capacitance value.

Or you can share the schematic with us, and tell us the part number of the output capacitors, we can check the GM and PM for you.

TPS55289 Design Calculation V1.0.xlsx

BRs,
Bryce

0 Weng Tzannbor 7 months ago in reply to Bryce Xun

Prodigy 40 points

TPS55289 related Circuit schematic can be reference as attached file.TPS55289 Circuit Schematic.pptx

0 Bryce Xun 7 months ago in reply to Weng Tzannbor

TI__Mastermind 28720 points

Hi Tzannbor,

I will look into this and reply to you these two days, thanks.

BRs,

Bryce

0 Bryce Xun 7 months ago in reply to Weng Tzannbor

TI__Mastermind 28720 points

Hi Tzannbor,

Thanks for reaching out.

1. What is the input voltage range? 6V-16V?

2. From the schematic, I can't see input and output capacitors and also the inductor. Could you share the full schematic of TPS55289-Q1?

3. Recommend to solder the EN pull-down resistor RB16.

4. MODE pin needs to connect with VCC or GND to select I2C address.

5. Check that SCL and SDA pins are both connected with VCC through pull-up resistors.

6. ISP and ISN pins should not be floating.

7. We need the part number of the output capacitors to check COMP parameters.

8. Connect all signal pins' ground with AGND, and connect AGND with PGND at VCC cap ground through net tie.

9. Follow the attached layout guideline and send to us for review when finished.

TPS55289 Layout Guide line.pdf

BRs,

Bryce

0 Weng Tzannbor 7 months ago in reply to Bryce Xun

Prodigy 40 points

1. What is the input voltage range? 6V-16V? -> 12V

2. Inductor.=4.7uH, Cin =117.4uF

3. Yes, Enable by VIN

4. MODE pin needs to connect with VCC or GND to select I2C address.
Yes
5. Check that SCL and SDA pins are both connected with VCC through pull-up resistors.
Yes
6. ISP and ISN pins should not be floating.
Ok

7. We need the part number of the output capacitors to check COMP parameters.

33KOhm / 10nF

8. Connect all signal pins' ground with AGND, and connect AGND with PGND

at VCC cap ground through net tie.

0 Bryce Xun 7 months ago in reply to Weng Tzannbor

TI__Mastermind 28720 points

Hi Tzannbor,

Thanks for the feedback,

1. From the schematic, I can't see input and output capacitors and also the inductor. Could you share the full schematic of TPS55289-Q1?

2. Recommend to solder the EN pull-down resistor RB16.

3. We need the ESR value and part number of the output capacitors to check COMP parameters.

4. Recommend to select the inductor with saturation current>8A.

5. Follow the layout guideline and send to us for review when finished.

BRs,

Bryce

0 Weng Tzannbor 7 months ago in reply to Bryce Xun

Prodigy 40 points

0 Bryce Xun 7 months ago in reply to Weng Tzannbor

TI__Mastermind 28720 points

Hi Tzannbor,

Sorry, I am confused about the block, this seems the PSpice simulation schematic, not the actual schematic, right?

And could you share the BOM or the part number of input and output capacitors if selected?

BRs,

Bryce

0 Weng Tzannbor 6 months ago in reply to Bryce Xun

Prodigy 40 points

PSpice simulation schematic can be run for load transient & Load steady only.

We want to simulate stable analysis about gain & phase margin.

On the other hand, the part number of input means that AL_Cap,100uF,35V,35HVHC100M+P,SUNCON,Green 4, right ?

Cin =47+68+2.35+0.05 =117.4F

0 Shipeng Cheng 6 months ago in reply to Weng Tzannbor

TI__Mastermind 18460 points

Hi Weng,

The calculation tool can show you gain & phase margin.

For Cin, If you consider ceramic DC derating, it's OK.

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TPS55289: TPS55289