TIDA-01606: Correct dead-time

Hi Mark,

You have a good point. Ideally, we would like to have consistent deadtime for these gate drivers.  In this reference design, we wanted to highlight our gate driver with DESAT protection as well as a basic isolated gate driver for this application.  We see customers sometime use basic iso gate drivers for all switches and rely on their current sensor for overcurrent protection.

When i was testing the new board, i evaluated the gate signals between the commutation pair and the switching node waveform during switching i found that 150 ns (i think you have a typo in your comment...you said "150 µs") would give us enough margin.  The idea is to avoid any shoot through current.

The deadband time can be measured from the falling edge to the rise edge of one switch to another switch.  you can confirm this with measuring the Vgs signals between two FETs.

Hi Kelvin,

For clarification:

In 3-level operation, Q1 and Q3 switch oppositely during the positive half-cycle (while Q2 is always off and Q4 is always on). If I set the controller with no deadtime, the controller’s PWM edges are perfectly opposite. However, due to the different propagation times of the gate drivers between Q1 (UCC21710 – 95ns) and Q3 (UCC5320 – 65ns), the edges overlap by 30ns when Q1 turns off and Q3 turns on. When Q3 turns off and Q1 turns on, there is a 30ns period where neither is on, leading to an asymmetry that can’t be fixed in software.

Result: With 150ns deadtime set on the controller for both rising and falling edges, the actual deadtime ends up being 120ns and 180ns.

I hope this makes sense. Ultimately, this time is sufficient to avoid shoot-through, but it would be ideal to keep it as small as possible for the best output voltage quality.

From this explanation, I have two questions:

1. Is there a way to influence the propagation time of the gate drivers?
2. Is 120ns (actual deadtime) sufficient?

Hi Team, seeking for additional support.

Thank you

Mark,

1. one way is to add propagation delay is adding more RC time constant at the driver input

2. around 100ns is sufficient

-Kelvin

are you working with a 1606 board right now?

this symmetry problem is not usually an issue since most customers use the same gate driver for all of their FETs in actual systems.

the 1606 is a reference design and we want to highlight a few different gate drivers (standard protection and basic isolated driver)

the net propagation delay becomes more important for very fast switching >200khz such as a matrix converter.  this affects the soft switching behavior & losses.