AFE7950EVM: AFE7950EVM+ZCU102

Paolo Artieri

Part Number: AFE7950EVM

Tool/software:

Hello

I had success bringing up the "TI ZCU102 8b10b" project, ZCU102_AFE79xx_8b10b_10Gbps, using the AFE7950EVM connected to the Xilinx ZCU102 development board.

My settings are the following:
FRef = 245.76
FadcRx = 2457.6
FadcFb = 2457.6
Fdac = 2457.6*4

LMFSHd = 24410
K = 16

LvdsSync= False
fpgaRefClk = 245.76

I modified some IP to change MGT ref clock, like GT and PLL, change the jesd_link_params.vh file and the constraints.xdc file properly.

I follow the TI204c-Setup.docx:

Power on ZCU102
Power on AFE7950EVM
Open Latte
Run setup.py
Run devInit.py
Run ConfigLmk.py
Program FPGA
Release master_reset_n -> 1
Release tx_reset -> 0
Run ConfigAfe.py
Release rx_reset -> 0

I see the qpll0 locked on hardware manager VIO1 but on Latte tools i see problems with RX link.

I already have the correct settings for JESD in jesd_link_params.vh.

`undef LANE_ADC_TO_GT_MAP
`define LANE_ADC_TO_GT_MAP {5,4,6,7,3,0,2,1}

`undef LANE_DAC_TO_GT_MAP
`define LANE_DAC_TO_GT_MAP {4,5,6,7,3,0,2,1}

What can be the problem for this?

over 1 year ago

0 David Chaparro over 1 year ago

TI__Mastermind 18811 points

Hi Paolo,

Just to confirm were the GPIO pins for the CMOS sync signals setup correctly to match the ZCU102 pins?

In the example reference design the script has the following GPIO mapping in order to use the correct pins on the ZCU102. Can you confirm that your AFE script has the same settings?

Regards,

David Chaparro

0 Paolo Artieri over 1 year ago in reply to David Chaparro

Prodigy 90 points

Hi David

yes I can confirm.

0 Paolo Artieri over 1 year ago in reply to Paolo Artieri

Prodigy 90 points

Sorry David but I see only now the difference in H7 GPIO, I will try it.

0 Paolo Artieri over 1 year ago in reply to David Chaparro

Prodigy 90 points

Hi David

I change the GPIO but now I have ither issue:

0 Paolo Artieri over 1 year ago in reply to David Chaparro

Prodigy 90 points

Any suggestion?

0 David Chaparro over 1 year ago in reply to Paolo Artieri

TI__Mastermind 18811 points

Hi Paolo,

In the jesd header file was the number of lanes updated from '8' to '4' and were the JESD parameters updated to match the new LMFS '48410'? Also, please note the the FPGA clocks should be set to LaneRate/80. The TI204c-IP User's Guide clocking section has more information on the clocking requirements if further details are required.

Regards,

David Chaparro

0 Paolo Artieri over 1 year ago in reply to David Chaparro

Prodigy 90 points

Hi David

my LMFS is 24410, why you sayd 48410?

I use ZCU102_AFE79xx_8b10b_10Gbps reference project with 64bit lane data width.
I try to set to 32 but there are a lot of errors regarding ILA and signal generator for lanes.
I modified it but still present error in bitstream generation.

Why cant set 32 bit for JESD, can you check please.

0 David Chaparro over 1 year ago in reply to Paolo Artieri

TI__Mastermind 18811 points

Hi Paolo,

Is there a specific reason for using 32 bit lane data width? Our recommendation is to use 64 bit and verify everything works.

The reason that I said the LMFS was 48410 is because the AFE79xx has a total of 4 Transmit (DAC/Tx), 4 Receive (ADC/Rx) and 2 Feedback (ADC/Fb) channels i.e. 4T4R2F. However, the AFE79xx is designed as two sub-chips (2T2R1F) within the device. Therefore, the parameters given in latte correspond to each sub-chip.

For example, if you are setting both sub-chips to '24410' then the overall LMFS (When 4T4R are enabled), which the FPGA should be configured to, is '48410'.

Regards,

David Chaparro

0 Paolo Artieri over 1 year ago in reply to David Chaparro

Prodigy 90 points

Hi David

I thinked is possible to modify it because is a define.
If I use 64 bit i cant achieve my goal, FPGA clock about 245.76MHz, is it correct?

My goal are the following:
FRef       = 245.76
FadcRx = 2457.6
FadcFb = 2457.6
Fdac       = 2457.6*4
LMFSHd = 24410
K   = 16
LvdsSync= False
fpgaRefClk   = 245.76

0 Paolo Artieri over 1 year ago in reply to Paolo Artieri

Prodigy 90 points

Hi David,

cam you give me an answer please.

Thanks

0 David Chaparro over 1 year ago in reply to Paolo Artieri

TI__Mastermind 18811 points

Hi Paolo,

I am not sure on the FPGA clock requirements as I do not see your lane rate or decimation/interpolation factors, but the FPGA clock is typically LaneRate/40 for 32 bit lane data width and LaneRate/80 for 64 bit lane data width.

Using the 64 bit width eases timing constraints since the clock required is slower.

Regards,

David Chaparro

Simulation, hardware & system design tools

Simulation, hardware & system design tools forum

AFE7950EVM: AFE7950EVM+ZCU102