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TIDA-00173: Some questions

Ryu Yamashita
Genius 3625 points
Part Number: TIDA-00173

Tool/software:

Hi team,

I have a few questions about this reference design.

  1. C1-C4 are components with a withstand voltage of 440VAC, is there any problem with inputting 690VAC?
    Also, what is the role of C4?
  2. The diodes (D1-D12) in the diode bridge are of large withstand voltage, is this amount of withstand voltage necessary?
    I am thinking that I can use one diode for each line or halve the withstand voltage, but is this correct?
  3. Please explain the reason for assuming that the power factor cosθ is 0.6 in “5.2.1 Input Diode Bridge”.
  4. I would like to know how to calculate 120uF (C11) to smooth the voltage generated from the winding of “5.2.5VDD Capacitor Selection (CDD)”.

Best Regards,
Ryu.

  • +1
    TI__Intellectual 1600 points

    Hi Ryu,

    Thank you for the questions.

    1. I agree with you that we will need to change these Y1 capacitors to higher voltage rating devices, such as 500Vac, in case the input phases voltage is 690Vac line-to-line.

    2. If Vdc bus reaches over 1000V, such as 690Vac*1.414*115%=1122V, two diodes in serial is necessary.

    3. In this kind of application, the auxiliary power supply often works in a light load condition, so that the power factor is assumed as 0.6 here.

    4. Often this C11 does not need strict calculation like it is for the C10. Usually twice or a little more than twice C10 may be OK.

    Best regards,

    Jerome Shan

  • 0 in reply to Jerome Shan
    Genius 3625 points

    Hi Jerome,

    Thanks for the reply.
    Can you tell me about C4 as well?

    Please add a little more information.

    Please add a little more information.
    Please explain why equation (14) in “5.2.6Current Sensing” results in 4.44 kohm, but the actual design (as implemented) is 1.0 kohm.
    In the reference design, I have selected ST's STF2N95K5, but the spec sheet says that it is 100% avalanche tested.
    Do we need to be avalanche tested when selecting other MOS?

    Best Regards,
    Ryu.

  • +1 in reply to Ryu Yamashita
    TI__Intellectual 1600 points

    Hi Ryu,

    1. C4 is used to provide a pass way to PE for high frequency noise on PGND. The static voltage between PGND and PE should be half of Vdc(bus) voltage. If Vdc(bus) voltage is over 800Vdc, we may need to use two such capacitors in serial to enhance voltage rating. Follow the capacitor provider's instruction for it: [https://product.tdk.com/system/files/dam/doc/product/capacitor/ceramic/lead-disc/specification/leaddiscspec_commercial_cd_en.pdf]

    2. As for the RLC selestion, there is a NOTE above the equation and it explained the reason for the 1kΩ:

    3. Although "avalanche tested" is not a must item, it does mean the device is more stronger and thus would be prefered, if possible.

    Best regards,

    Jerome Shan