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TPS63000: TPS63000 loop stability, current sink in feedback divider.

Michael Klimek
Prodigy 40 points
Part Number: TPS63000

Tool/software:

I have a design utilizing TPS63000 to generate an adjustable voltage output between 1.2 and 5.5V. 

To allow for the voltage output adjustability the lower resistor of the voltage divider feeding the FB pin is tied to a current sink.  The resistor between output and feedback is 16.2k due to the current sink.
This has worked well for a number of years, however, recent batches of boards are showing instability, the output of the regulator periodically oscillates.

As a first step, I would like to verify the phase margin of the nominal design but I am unable to generate a bode plot with Webench, am I just not seeing this option or is it not available for the TPS63000?

On a side note, the use of the current sink may reduce the gain margin the the regulator feedback loop, any suggestions on compensation?

Nominal inductor value is 3.3uH, reducing it to 2.2uH helps with stability.

Likewise, output is a pair of 22uF caps, increasing their rated voltage (and thus increasing derated value) as well as increasing nominal value helps with stability.

Thanks.

  • 0
    TI__Mastermind 18700 points

    Hi Michael，

    Michael Klimek said:
    am I just not seeing this option or is it not available for the TPS63000?

    I think so.

    Compared with the circuit that "worked well for a number of years", are there any BOM changes in the current circuits? Especially in the inductor and Cout.

    By the way, decrease the inductance will push the right-half-zero far away, and increase the effective output capacitance (for example, increase the voltage rating while keeping the same rated capacitance) can reduce the cross over frequency. Both ways are the generally used methods to increase the phase margin and improve the stability.

    Regards

    Lei 

  • 0 in reply to Lei Zhong
    Prodigy 40 points

    Hi Lei,

    The inductor has stayed the same, the capacitors were replaced with one having matching characteristics, one question being the ESR, it's likely a little higher on the ones currently populated.  

    I am suspecting that the current sink which replaces the lower resistor of the voltage divider messes with the loop gain of the regulator, also; however this has been a constant all along.

    _Michael

  • 0 in reply to Michael Klimek
    Prodigy 40 points

    I created an extreme case with a very large inductor and little output capacitance with assumption that it would at least generate a stability warning in Webench as shown in this video: https://www.youtube.com/live/BpVN0zD85d4?feature=shared&t=1838 but I see no such warning.  I also don't see any options regarding phase margins within the design.  What am I missing?  

    Link to design mentioned in this reply:
    https://webench.ti.com/appinfo/webench/scripts/SDP.cgi?ID=BA618EDB639C1783

    Thanks.

    _Michael

  • 0 in reply to Michael Klimek
    TI__Mastermind 18700 points

    Hi Michael，

    Higher ESR means smaller zero caused by the ESR. So it is possible to make the cross frequency increase and the phase margin smaller.

    I think slightly increase the effective output capacitance can make the loop stable again, as you mentioned already.

    For the webench simulation, whether the instability risk can be detected heavily depends on the the model. I think this model doesn't have this function.

    Well, you may try a load or line transient to estimate the phase margin by whether there are rings in time domain.

    Regards

    Lei.