PMP23366: Why we need huge capacitance (47uF x 3) after PD chip

During transition, the VDD-RTN voltage will drop so you need enough hold up cap (especially if there is a voltage difference between the two PoE ports). I recommend you keep what is shown in the reference design as it has been tested. thanks!

Hi Felix, unfortunately i do not recommend this. VDD-RTN cap must be able to minimize the amount of inrush when the second port gets plugged in, otherwise, the PD controller will fail inrush spec.

does it need to have smooth transition (no drop in output voltage) when one port is plugged in and the other port gets plugged? then i suggest you keep the current design in your schematic and unpopulate the components during your testing to prove it out on your board. as i recall, we tried alot of different approaches and our implementation worked well.