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UCC14141-Q1: UCC21710-Q1 Gate Driver Shutdown Issue Above 170V Input

Ajay R
Prodigy 60 points
Part Number: UCC14141-Q1
Other Parts Discussed in Thread: UCC21710-Q1

Tool/software:

Dear Team,

We are using the UCC21710-Q1 gate driver in a DC-DC converter with a full-bridge topology. The gate driver is powered by a UCC14141QDWNRQ1 DC-DC module, which provides +15V and -4V. The main switches are IPTC011N08NM5 SiC MOSFETs.

We are experiencing a consistent issue where the gate driver shuts down when the DC input supply voltage exceeds approximately 170V. This behavior is unexpected, and we have taken several troubleshooting steps without success.

Key Design and Observations:

  • Gate Driver Power Supply: The UCC21710-Q1 is powered by the UCC14141QDWNRQ1 module.

  • Protection Features: We have disabled the overcurrent (OC) and analog input (AIN) pins by tying them to GND. The APWM pin is floating. We also removed the D35 diode to disable drain voltage sensing.

  • Gate Resistors: The gate turn-on and turn-off resistors are 10Ω and 2Ω, respectively.

  • Troubleshooting: We've observed that changing the R_LIM resistor on the UCC14141QDWNRQ1 from 75Ω to 133Ω allowed the input voltage to reach 175V before shutting down, but we are unable to go higher. This suggests the issue may be related to the power supply's current limit.

We have attached the relevant schematic images for your review. We suspect the shutdown is due to an undervoltage lockout (UVLO) condition on the UCC21710-Q1, potentially caused by the power supply struggling to maintain a stable output at higher input voltages.

Any guidance you can provide on this matter, especially related to potential power supply instability, ground reference issues, or other protection mechanisms, would be greatly appreciated.

Thank you for your time and assistance.


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Best regards,

Ajay S Ruli
Systems Engineer- ALTEN GT
  • 0
    TI__Genius 10200 points

    Hello,

    Please expect a delay in responses due to US holiday.

    Thanks.

  • 0
    TI__Expert 8065 points

    Hi Ajay,

    I looked into the gate driver portion of the schematics, it looks good, I don't see any issues. I believe that RDY and FLT are pulled up to VCC with 5K resistance. (not shown in the schematics ).

    When you say that the Gate driver shutdown - what are the behaviors you are observing. (RDY/FLT going low along with OUT).

    Is it possible to capture the waveforms,

    • FLT, RDY, OUT, INP during the failure (H to L ) transition.
    • If it is RDY (need to capture RDY, VCC, VDD, VEE when RDY falling low.

    All the captures need to be close to gate driver with high BW probe and scope.

    I will assign this ticket to isolated bias team so that they can help with the schematic review.

    Thanks

    Sasi

      

  • 0 in reply to Sasikala Thangam
    TI__Expert 8065 points

    Hi Ajay,

    Based on inputs from Isolated Bias team, we have additional feedback as shown below.

    Summary of updates needed below:

    Detailed report and the template to achieve the needed information is attached below,

    Feedback report

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