• State TI Thinks Resolved
  • Locked Locked
  • Replies 7 replies
  • Answers 2 answers
  • Subscribers 38 subscribers
  • Views 133 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

PSPICE-FOR-TI: Regarding the IBIS model for ADC12DC105

Kyohei
Expert 1701 points
Part Number: PSPICE-FOR-TI
Other Parts Discussed in Thread: ADC12DC105

Tool/software:

Hi team,

My customer is considering adopting the ADC12DC105, and during the evaluation process, they would like to use an IBIS model.

I checked with the Data Converter BU, and since this is an older product, an IBIS model is not available.

Is it possible to create a new IBIS model for this device, or alternatively, is there another ADC device with a single-ended clock input that has an available IBIS model?

Best regards,

Kyohei

  • 0
    TI__Mastermind 41240 points

    Hi Kyohei,

    IBIS models are used and created for general purpose IO and digital outputs.

    If the customer is interested in the clock input, then they should really use sparameters for this.

    With that, what is the main concern of the ADC12DC105 clock input? What do they plan to use to drive the clock input.

    Lets start there and see if I can help that way. 

    Regards,

    Rob

  • 0 in reply to Rob Reeder
    Expert 1701 points

    Hi Rob,

    Thank you for your support.

    Regarding the question below, we have confirmed with the customer and are now providing our answer.

    ＞With that, what is the main concern of the ADC12DC105 clock input?

    Objective: To design optimal PCB patterns and determine appropriate damping resistor values, taking into account signal reflection and attenuation.

    ＞What do they plan to use to drive the clock input.

    This is a PLL signal from the FPGA (100 MHz clock).

    Best regards,

    Kyohei

  • 0 in reply to Kyohei
    TI__Mastermind 41240 points

    Hi Kyohei,

    If they plan to use an FPGA for the clock at 100MHz, this will destroy the performance of the ADC anyway due to the FPGA high jitter.

    To me, this is a bigger concern.

    Is this a DC application or what BW are they planning to use?

    Thanks,

    Rob

  • 0 in reply to Rob Reeder
    Expert 1701 points

    Hi Rob,

    Thank you for your support.

    I have confirmed with the customer. The bandwidth of the analog signal to the ADC will be up to approximately 10 MHz.

    BR,

    Kyohei

  • 0 in reply to Kyohei
    TI__Mastermind 41240 points

    Hi Kyohei,

    Should be okay, but if the noise is too high, meaning the SNR or dynamic range is low, then they made need to investigate improving the sampling clock and not use the FPGA as a sampling clock.

    Regards,

    Rob

  • 0 in reply to Rob Reeder
    Expert 1701 points

    Hi Rob,

    Thank you for your support.

    Regarding the above matter, we will share the information with the customer.
    As for the IBIS model, considering the points mentioned above, is it correct to assume that verification using the IBIS model is not necessary, and that the IBIS model will not be provided?

    Best regards,

    Kyohei

  • 0 in reply to Kyohei
    TI__Mastermind 41240 points

    Hi Kyohei,

    Correct. Typically IBIS models are created for checking the interface for digital inputs and outputs.

    On a ADC or DAC, the clock is not a digital signal. It is an analog signal.

    We just don't have the IBIS models available for this much older device unfortunately.

    Regards,

    Rob