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PSPICE-FOR-TI: Regarding the IBIS model for ADC12DC105

Kyohei
Expert 1400 points
Part Number: PSPICE-FOR-TI
Other Parts Discussed in Thread: ADC12DC105

Tool/software:

Hi team,

My customer is considering adopting the ADC12DC105, and during the evaluation process, they would like to use an IBIS model.

I checked with the Data Converter BU, and since this is an older product, an IBIS model is not available.

Is it possible to create a new IBIS model for this device, or alternatively, is there another ADC device with a single-ended clock input that has an available IBIS model?

Best regards,

Kyohei

  • 0
    TI__Mastermind 37960 points

    Hi Kyohei,

    IBIS models are used and created for general purpose IO and digital outputs.

    If the customer is interested in the clock input, then they should really use sparameters for this.

    With that, what is the main concern of the ADC12DC105 clock input? What do they plan to use to drive the clock input.

    Lets start there and see if I can help that way. 

    Regards,

    Rob

  • 0 in reply to Rob Reeder
    Expert 1400 points

    Hi Rob,

    Thank you for your support.

    Regarding the question below, we have confirmed with the customer and are now providing our answer.

    ＞With that, what is the main concern of the ADC12DC105 clock input?

    Objective: To design optimal PCB patterns and determine appropriate damping resistor values, taking into account signal reflection and attenuation.

    ＞What do they plan to use to drive the clock input.

    This is a PLL signal from the FPGA (100 MHz clock).

    Best regards,

    Kyohei

  • 0 in reply to Kyohei
    TI__Mastermind 37960 points

    Hi Kyohei,

    If they plan to use an FPGA for the clock at 100MHz, this will destroy the performance of the ADC anyway due to the FPGA high jitter.

    To me, this is a bigger concern.

    Is this a DC application or what BW are they planning to use?

    Thanks,

    Rob