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TPA3136D2: Confirmation on 100% Duty Cycle Capability During Clipping

Zylon
Prodigy 20 points
Part Number: TPA3136D2

Tool/software:

Hello,

I am working with TPA3136D2 and would like to clarify a question regarding its duty cycle behavior during output clipping.

According to the datasheet:

9.1 Overview
"These capacitors ensure sufficient energy storage, even during clipped low frequency audio signals, to keep the high-side power stage FET (LDMOS) fully turned on during the remaining part of its ON cycle."

9.3.3 PLIMIT
The PLIMIT circuit sets a limit on the output peak-to-peak voltage. The limiting is done by limiting the duty cycle to a fixed maximum value. The limit can be thought of as a "virtual" voltage rail which is lower than the supply connected to PVCC. The "virtual" rail is approximately four times the voltage at the PLIMIT pin. The output voltage can be used to calculate the maximum output power for a given maximum input voltage and speaker impedance.

From my measurements, it appears that during clipping, the OUTNL/OUTNR duty cycle can reach 100%. I would like to confirm whether this IC is indeed capable of achieving a full 100% duty cycle.

My circuit configuration is as follows:

  • AVCC = 12 V

  • RL = 4 Ω

  • PLIMIT = 1/2*GVDD

  • BTL mode = Mono PBTL mode

  • Speaker output power ≈ 3 W

Attached are three waveform screenshots showing the duty cycle approaching 100% during clipping. Could anyone confirm if my observation is correct or if there is something I might be overlooking in this configuration?

Thank you in advance for your insights!

  • 0
    TI__Genius 17820 points

    Hello,

    No due to the architecture of this amplifier it should not be able to output 100% duty cycle / DC. Are you using the EVM? Where + how are you measuring? 

    Regards,
    Sydney Northcutt

  • 0 in reply to Sydney Northcutt
    Prodigy 20 points

    Hello,

    I would like to clarify and correct my previous description. The actual output power in our test is 5W, not 3W as I mentioned earlier.

    Also, please note that we are not using the EVM. The testing was performed on our own PCB. In the waveforms I shared earlier, the blue trace represents the 12V supply, while the green and purple traces represent the L and R outputs. As you can see, both channels are running at a duty cycle very close to 100%, which is the part I find confusing and would like to confirm with you.

    Thank you for your support.

    Best regards,
    Zylon

  • +1 in reply to Zylon
    TI__Genius 17820 points

    Hi Zylon,

    Oh sorry I misspoke I was thinking the device had a different modulation scheme. This device is using BD modulation - so 100 % duty cycle is possible but should be avoided. Essentially this is pushing the output stage outside of the linear region so it is not ideal. 

    Regards,
    Sydney Northcutt

  • 0 in reply to Sydney Northcutt
    Prodigy 20 points

    Hi Sydney,

    Thanks for the clarification. I have a few follow-up questions regarding the 100% duty cycle case:

    If the device goes into 100% duty cycle during clipping, does this only affect linearity and sound quality, or could it also impact device reliability/lifetime?

    1. Should occasional 100% duty cycle operation be considered normal behavior of the device under clipping, or does it indicate that design parameters (such as PLIMIT setting, supply voltage margin, or input amplitude) should be adjusted?

    2. Are there recommended design practices to minimize or avoid entering 100% duty cycle in real applications?

    Thanks again for your support.

    Best regards,
    Zylon

  • +1 in reply to Zylon
    TI__Genius 17820 points

    Hi Zylon,

    The device should have protections that avoid the amplifier from damage, but this is not a necessarily good point of operation for the amplifier and this does significantly impact sound quality. 

    1. You want to design the amplifier configuration limiting clipping as much as possible. Ideally completely. Various things can be considered to fix and or prevent clipping such as reducing gain, increasing PVCC, or adjusting the PLIMIT. 

    2. To avoid clipping you should set PVCC such that there is sufficient headroom above your largest output signal. Essentially you can considering your input signal level + gain and then convert that to a peak voltage. You PVCC should then be above this value.

    Regards,
    Sydney Northcutt