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PMP8740: Active clamp leg and dead-time

Andres Gomez
Intellectual 450 points
Part Number: PMP8740

Tool/software:

Hi.

I saw you guys do not implement an active clamp leg for the PSFB, instead you used regular snubber. Do you have any document about the control of the actvie clamp leg? I have been reading documents on the selection of the capacitor and mosfets, but nothing about the control.

Additionally, do you have any document that explain the delay time circuit from PMP8740?

Thank you in advance

  • 0
    Intellectual 450 points

    This is my ringing right now in my simulation when I use the EPC GaN pspice models.




    Those ringing is the same as the traditional Full bridge that I have worked before. I really need to reduce that ringing but I don't want to use RCD since my power losses are going to increase

  • 0 in reply to Andres Gomez
    TI__Expert 5895 points

    Hi Andres,

    I didn't implement active clamp on PMP8740 sync-rectification. I relied on the primary side clamping diodes D7, D10. In fact, without these diodes there is pretty much ringing on output diodes or sync-FETs, because of the secondary side leakage inductance, when leveraging this inductance on primary side as shim inductor (which extends the load range where the converter achieves ZVS). My suggestion is here to have a very well coupled transformer, minimizing its leakage inductance, and adding an external shim inductor (in PMP8740 it's T7. This inductor, In addition to D7 and D10, create a primary side clamping (the energy is reverted back to input capacitors) which translates into lower spike and ringing on secondary side. I suggest to simulate this transformer arrangement by adding the shim inductor and diodes.

    Regarding the the delay time circuit from PMP8740, I just referred to the UCC2895x datasheet and its excel calc-sheet.

    Thanks,

    Roberto

  • 0 in reply to Roberto S.
    Intellectual 450 points

    ok, I'll try that. The issue is I need a ZVS from 50% to 100% in an extent Vin range. From 82V to 135V. I am barely complying with ZVS at 135V at half-load so decreasing the leakage inductor is going to be with a penalty. Let me try also selecting another GaN that has less Coss. This one has 670pF

  • 0 in reply to Andres Gomez
    TI__Expert 5895 points

    Goo, just let me know how it behaves. Anyway, I believe the higher the extra (shim) inductor, the wider ZVS range you get. In addition, with higher inductance, there is less spike on secondary side...