PMP23391: Current Sense topology

a kind reminder ..

Hi John, 
1. R103 you mean R108, the diodes function and numbers I think you mean the opposite correct ?
D104 will be forward biased since the voltage on the cathode should drop to compensate for the current going into the transformer ?
when D102 & D103 reset the core of the transformer should they be forward or reverse biased ?

2. so if in my design I am not expecting more than 10A on the output, these 4 diodes should be the optimum for my push pull and flyback design ?

BR,
Mohamed

Hi Mohamed,

1. Yes, that was my mistake I was using the designators from the PMP23391 schematic on the web which is rev C. I believe you have the Rev D version for testing. The stored energy conducts through D102 and D103 in your schematic which would make them forward biased during the reset time.

2. This would be okay for a push-pull topology, but a flyback would be different... Do you have more information on the flyback design, controller? Placement on primary or secondary ground?

Hi John, 
2.1 the PWM controller will be placed on SEC side, I will be using TPS7H5001-SP & TPS7H6003 with SR. why would it be different for a flyback ?
2.2 based on my estimation we might get up to 9A worst case scenario with 6A nominal current, is a push pull needed for that or can a flyback also be used ?
how to make the decision based on available trade-off. 
2.3 with SR, I have seen these two Sch which look different than a normal Flyback or push pull for the secondary side. does it look like this to avoid using the bootstrap effect of the gate driver, since your are driving the SR FETs with respect to GND ? 





2.4 all the above Schematics are used to generate +ve voltages, since we need +ve and -ve voltage at the output, how would the Schematic be updated to accommodate the negative voltage ? 

Thanks alot for your support!
Mohamed 

Hi Mohamed,

2.1 That makes sense for implementation. I was curious because we have a single driver + controller device TPS7H5020-SEP. This would not be applicable for a synchronous design however.

2.2 I would recommend a forward topology for that design. Are you in contact with your TI FAE? I am developing a 28 to 5V, 15A design that utilizes a forward topology that gets good efficiency with minimal BOM count. Your FAE can help share information on that design. In regards to flyback vs. push-pull, a flyback will start to lose it's efficiency due to high peak currents. Being synchronous helps, but typically we do not have high output current on a flyback design. A push-pull design would work, the down-side to this topology is the size and BOM count since it requires two FETs on the primary and secondary side. Flyback would optimize for size, push-pull optimizes for performance, Forward is a balance of the two topologies.

2.3 Those schematics do not seem to have the feedback set up for isolated power delivery. Typically we have the controller on the secondary ground so that the output voltage can be sensed directly. In those designs they would need a way to isolate the control signal from secondary to primary. 

2.4 The correct solution depends on the loading conditions. What are the specific ve+/- voltage and expected loads? With a flyback it is possible to have good regulation if they are the same magnitude voltage. See EDN Power Tip #85: https://www.edn.com/power-tips-85-adding-a-single-capacitor-to-improve-cross-regulation-in-dual-output-flyback-power-supplies/

Let me know if you have any questions on this.

Thanks,

John 

Hi John, 
2.2 I think our current need is for SMPS with SR & +ve & -ve voltage around 6.1V or more ( then feed it to PR to reach 5mvpp Ripple ) and with a max current around 4,5A. can this forward be adjusted to have +ve -ve output both with SR ? 
2.4 so our need currently is to have +-6.1V from 28V, where +6.1V with 2.6A max and -6.1V with 130mA max. if we are really targeting 85-90% efficiency can we do that without SR for these loads ? what would be the best strategy ?

Thanks! 
Mohamed

Hi John, 
2.2 the -ve output has 800mA max current and +ve output has 6.3A max current, so the loading is not similar. Moreover this converter must supply 2 equipment each one has its own GND, so two GND in total and 6 Voltage rails 2 of them are negative.
to avoid complexity of having two gate drivers on the SEC side can we use one gate driver for both equipment, I have seen you have done something similar with forward converter would it work with flyback with 4 windings in the output the first two sharing the same GND one positive regulated with SR and one negative unregulated only with Diode, the last two excatly as before but with different GND.   

since we will need anyways PR to achieve that high ripple (5mVpp). in that case as well I should not worry about -ve rail regulation since it is drawing less amount of current and will be regulated by a post regulator, how does this sound ? 

2.4 this coupled inductor seems like a good idea, is it crucial for cross regulation ? how would its calculation take place ? is it the same as separate inductors on the output ? 

Thanks! 
Mohamed

Hi Mohamed,

2.2 That makes sense, the configuration you mentioned will allow for SR which helps for the conduction losses on the secondary. The post regulation with a linear regulator would help out with both the accuracy and ripple rating.

2.4 Yes the coupled inductor is very important for cross regulation. Even with post-regulation you still want to keep the -ve output from flying to high, leading to high conduction losses. In regards to calculation, I would consider the current stresses assuming the entire load on one winding for the total inductance (6.3A + 0.8A). Then the conductors can be sized down to accommodate the current stresses for their individual loading conditions (6.3A for +ve, then 0.8A for -ve).

Thanks,

John